Patents by Inventor Hernan A. Castro

Hernan A. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150212032
    Abstract: Described are devices and methods for detecting the match quality and concentration of analytes binding to an electrode surface. The devices utilize a clock to measure capacitance change as a function of time and a temperature controller to measure the capacitance change as a function of temperature.
    Type: Application
    Filed: April 3, 2015
    Publication date: July 30, 2015
    Inventors: Gordon HOLT, Hernan CASTRO, Brandon BARNETT
  • Publication number: 20150187417
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 2, 2015
    Inventor: Hernan Castro
  • Publication number: 20150179258
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 25, 2015
    Inventor: Hernan A. Castro
  • Patent number: 9025398
    Abstract: For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Everardo Torres Flores, Hernan A. Castro, Jeremy M. Hirst
  • Patent number: 8999724
    Abstract: Described are devices and methods for detecting the match quality and concentration of analytes binding to an electrode surface. The devices utilize a clock to measure capacitance change as a function of time and a temperature controller to measure the capacitance change as a function of temperature.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Gordon Holt, Hernan Castro, Brandon Barnett
  • Publication number: 20150074326
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hernan Castro
  • Publication number: 20150070960
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • Publication number: 20150063021
    Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman
  • Publication number: 20150055408
    Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Inventors: Hernan Castro, Timothy C. Langtry, Richard Dodge, IIya Karpov
  • Patent number: 8953387
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Hernan Castro
  • Patent number: 8917534
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 23, 2014
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • Publication number: 20140372713
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Publication number: 20140362650
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventor: Hernan Castro
  • Publication number: 20140339493
    Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.
    Type: Application
    Filed: June 13, 2014
    Publication date: November 20, 2014
    Inventors: Fabio Pellizzer, Hernan A. Castro, Eddie T. Flores
  • Patent number: 8891319
    Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Hernan Castro, Timothy C. Langtry, Richard Dodge, Ilya Karpov
  • Patent number: 8891280
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Publication number: 20140334237
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Application
    Filed: June 30, 2014
    Publication date: November 13, 2014
    Inventors: Jeremy Hirst, Hernan Castro, Stephen Tang
  • Publication number: 20140239512
    Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Hernan A. Castro, Everardo Torres Flores
  • Patent number: 8785314
    Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Hernan A. Castro, Eddie T. Flores
  • Patent number: 8767482
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Hirst, Hernan Castro, Stephen Tang