Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.

Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Abstract: For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Abstract: Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers and devices and methods for synthesizing and detecting binding to the polymer on a common integrated device surface are described.

Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

Abstract: Asymmetric select and deselect drivers are provided for select lines driven to a resistive cross-point memory array. An address may be fully decoded to determine the active select driver, but a partial decode may be performed for the deselect drivers. Some embodiments may manage the odd and even deselect drivers as two sets of drivers and some embodiments may use sub-optimal transistors as the deselect drivers to save die area. Some embodiments may implement the deselect drivers as modified memory elements to reduce die area further.

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract: A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.

Abstract: Asymmetric select and deselect drivers are provided for select lines driven to a resistive cross-point memory array. An address may be fully decoded to determine the active select driver, but a partial decode may be performed for the deselect drivers. Some embodiments may manage the odd and even deselect drivers as two sets of drivers and some embodiments may use sub-optimal transistors as the deselect drivers to save die area. Some embodiments may implement the deselect drivers as modified memory elements to reduce die area further.

Abstract: Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers and devices and methods for synthesizing and detecting binding to the polymer on a common integrated device surface are described.

Abstract: Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell.

Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices.

Abstract: Embodiments disclosed herein may relate to controlling a discharge of a capacitive element coupled to a phase change memory cell to produce a specified state in the phase change memory cell.

Abstract: Embodiments of the invention provide methods for detecting molecular recognition events electronically and optically. Methods according to embodiments of the invention provide a nucleic acid molecule that hybridizes to a first probe nucleic acid molecule attached to an electronic detector wherein the second nucleic acid molecule comprises two regions. The two regions of the second nucleic acid molecule consist of a region that is complementary to the probe nucleic acid and a distal region that is not complementary to the first probe nucleic acid molecule. The hybridization reaction is detected electronically. A third nucleic acid molecule having an attached optically detectable label is hybridized to the distal region of the second nucleic acid molecule and the label is detected optically. Methods according to embodiments of the invention are useful, for example, to validate and quantify electronic detection methods.

Abstract: A phase change memory using an ovonic threshold switch selection device may be programmed from one state to another by first turning on the ovonic threshold switch. After the voltage across the cell has fallen, the cell may then be biased to program the cell to the desired state.

Abstract: Described are devices and methods for detecting the match quality and concentration of analytes binding to an electrode surface. The devices utilize a clock to measure capacitance change as a function of time and a temperature controller to measure the capacitance change as a function of temperature.

Abstract: Embodiments of the invention provide methods for detecting molecular recognition events electronically and optically. Methods according to embodiments of the invention provide a nucleic acid molecule that hybridizes to a first probe nucleic acid molecule attached to an electronic detector wherein the second nucleic acid molecule comprises two regions. The two regions of the second nucleic acid molecule consist of a region that is complementary to the probe nucleic acid and a distal region that is not complementary to the first probe nucleic acid molecule. The hybridization reaction is detected electronically. A third nucleic acid molecule having an attached optically detectable label is hybridized to the distal region of the second nucleic acid molecule and the label is detected optically. Methods according to embodiments of the invention are useful, for example, to validate and quantify electronic detection methods.

Abstract: A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.

Abstract: A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.