Patents by Inventor Hidehiro Fujiwara
Hidehiro Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240251540Abstract: An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. Each memory cell among the plurality of memory cells includes complementary field-effect transistor (CFET) devices.Type: ApplicationFiled: May 30, 2023Publication date: July 25, 2024Inventors: Kao-Cheng LIN, Hidehiro FUJIWARA, Yen Lin CHUNG, Wei Min CHAN, Yen-Huei CHEN
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Publication number: 20240243105Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).Type: ApplicationFiled: March 28, 2024Publication date: July 18, 2024Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
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Patent number: 12029023Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.Type: GrantFiled: April 20, 2023Date of Patent: July 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20240212749Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.Type: ApplicationFiled: March 11, 2024Publication date: June 27, 2024Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20240212747Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.Type: ApplicationFiled: March 11, 2024Publication date: June 27, 2024Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
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Publication number: 20240201951Abstract: A method for performing a shift last multiplication and accumulation (MAC) process. A processing circuit can multiply a first input by a first bit of a second input to obtain a first intermediate output. The processing circuit can multiply a third input by a first bit of a fourth input to obtain a second intermediate output. The processing circuit can sum the first and second intermediate outputs to obtain a first sum. The processing circuit can multiply the first input by a second bit of the second input to obtain a third intermediate output. The processing circuit can multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. The processing circuit can sum the third and fourth intermediate outputs to obtain a second sum. The processing circuit can generate an output by accumulating the first sum and the second sum.Type: ApplicationFiled: June 9, 2023Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kinshuk Khare, Hidehiro Fujiwara, Wei-Chang Zhao, Haruki Mori
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Publication number: 20240203488Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: ApplicationFiled: February 28, 2024Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro FUJIWARA, Chih-Yu LIN, Sahil Preet Singh, Hsien-Yu PAN, Yen-Huei CHEN, Hung-Jen LIAO
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Publication number: 20240179884Abstract: An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hidehiro FUJIWARA, Yi-Hsin NIEN, Hung-Jen LIAO
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Patent number: 11997843Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.Type: GrantFiled: August 9, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Chia-En Huang, Yen-Huei Chen, Yih Wang
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Patent number: 11989046Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: February 6, 2023Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Patent number: 11978723Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).Type: GrantFiled: November 30, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
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Publication number: 20240145385Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.Type: ApplicationFiled: February 16, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Patent number: 11961554Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.Type: GrantFiled: December 11, 2020Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
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Patent number: 11948627Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20240105241Abstract: Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.Type: ApplicationFiled: February 16, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
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Publication number: 20240094943Abstract: A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N?1, and values of the second sequence decrement from N?1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Hidehiro FUJIWARA, Haruki MORI, Wei-Chang ZHAO
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Publication number: 20240096757Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
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Patent number: 11935586Abstract: A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.Type: GrantFiled: February 11, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao
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Patent number: 11929116Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.Type: GrantFiled: January 23, 2023Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20240079052Abstract: A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.Type: ApplicationFiled: March 24, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nikhil PURI, Venkateswara Reddy KONUDULA, Teja MASINA, Yen-Huei CHEN, Hung-Jen LIAO, Hidehiro FUJIWARA