Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A device and method of operating the device are disclosed. In one aspect, a device includes receive a first bit of first input data and a plurality of second bits of second input data. The processing circuit generates a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data. The processing circuit generates a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A semiconductor device includes a first memory cell in a 4CPP architecture; a second memory cell formed in the 4CPP architecture and physically disposed next to the first memory cell along a first lateral direction; a first word line extending along the first lateral direction and operatively coupled to the first memory cell; a second word line extending along the first lateral direction and operatively coupled to the first memory cell; a third word line extending along the first lateral direction and operatively coupled to the second memory cell; a fourth word line extending along the first lateral direction and operatively coupled to the second memory cell; a first bit line extending along a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first memory cell; and a second bit line extending along the second lateral direction and operatively coupled to the second memory cell.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: A memory device is provided. The memory device comprises a memory cell array, a first control circuit, a second control circuit, a third control circuit, a first pair of bit lines, a second pair of bit lines, and a first conductive line. The memory cell array has a plurality of memory cells, each of the memory cells comprising a first port and a second port. The first pair of bit lines electrically connect the first control circuit, the first port of each of the memory cells, and the second control circuit. The second pair of bit lines electrically connect the third control circuit and the second port of each of the memory cells. The first conductive line electrically connects the first control circuit and the second control circuit, such that the first control circuit is configured to control the second control circuit via the first conductive line.

Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

Abstract: A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

Abstract: A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply-accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply-accumulate operation using the second portion and the third portion.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A memory cell array includes a first bank of memory cells, a second bank of memory cells adjacent to the first bank of memory cells, a first set of bit lines and a second set of bit lines. The first set of bit lines extend in a first direction, is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. The second set of bit lines extend in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate.

Abstract: A memory device is provided. The memory device comprises a memory cell array, a first control circuit, and a second control circuit. The memory cell array has a plurality of memory cells, wherein each of the plurality of memory cells comprises a first port and a second port. The first control circuit is disposed on a first side of the memory cell array and is arranged to electrically connect to the plurality of first ports. The second control circuit is disposed on the first side of the memory cell array and is arranged to electrically connect to the plurality of second ports. The plurality of first ports are different from the plurality of second ports.

Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.

Abstract: An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. Each memory cell among the plurality of memory cells includes complementary field-effect transistor (CFET) devices.