Patents by Inventor Hideki Harada

Hideki Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6414844
    Abstract: A portable information processing apparatus is configured to dissipate heat generated in a cabinet mainly from a part which a user hardly touches, and thus the temperature at a palm rest is suppressed. The cabinet includes a heat conducting spacer 16 provided over a heat-generating component 15 to conduct heat thereof, a heat absorption area 10ah to absorb the heat of the heat-generating component 15 through the heat conducting spacer 16, and a heat conduction obstructing area 10rb provided on a heat conduction path between the heat absorption area 10ah and the palm rest 11 to reduce a cross-sectional area of the heat conduction path. Accordingly, heat conduction from the high-temperature heat generating component 15 to the palm rest 11 is restricted, and thus the temperature of the palm rest 11 can be limited.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: July 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Shimada, Hideki Harada, Junichi Kubota, Akihiro Kuranaga
  • Patent number: 6381129
    Abstract: An extension device 5 is engaged in a connector provided on one side of a lower case 102 of a cabinet 100 of an PIP apparatus PI. An adjustable foot 6 is provided on the bottom surface 102u to adjust the extension device 5 and the cabinet 100 in height. Therefore, the cabinet 100 can be horizontally placed on a plane. When the extension device 6 is approximately equal in height to the lower case 102, the adjustable foot is retracted into the lower case 102. Therefore, the thickness of the PIP apparatus PI can be minimized.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: April 30, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Shimada, Hideki Harada, Junichi Kubota, Akihiro Kuranaga
  • Publication number: 20020047033
    Abstract: A holder allowing a portable terminal to be held selectively on a waist or thigh is provided. The holder for a portable terminal comprises an accommodating unit for accommodating the portable terminal, and plural wearing units for having the accommodating unit worn on a body. The plural wearing units include a thigh fixing band worn on the thigh, a belt fixing band suspended on a waist belt, and a waist belt band having only an inserting unit slightly wider than the width of the belt. The units are attached to the accommodating unit.
    Type: Application
    Filed: April 25, 2001
    Publication date: April 25, 2002
    Inventors: Hideki Harada, Naoyuki Ito, Nobuhiro Ide
  • Publication number: 20020047028
    Abstract: A holder for a portable terminal allows the terminal to be used stably even if the terminal is mounted on a forearm, and prevents a heat from the portable terminal form being conducted directly. The holder for a portable terminal comprising a holding unit for holding the portable terminal detachably along the longitudinal direction of the forearm, a first mounting unit for fixing the holding unit to the forearm, and a second mounting unit for fixing the holding unit to a thumb or palm. The holding unit includes a forearm pad made of highly insulating material. The second mounting unit includes a palm band and a thumb band for fixing the holding unit to the palm and thumb, respectively.
    Type: Application
    Filed: April 25, 2001
    Publication date: April 25, 2002
    Inventors: Hideki Harada, Naoyuki Ito, Nobuhiro Ide
  • Patent number: 6334802
    Abstract: An electrode for a display device, including a laminate of an underlying layer, a conductive layer and a protective layer formed on a substrate in this order from the substrate side in such a manner that at least the conductive layer is completely covered by the protective layer, the underlying layer and the protective layer being composed of a metal which is hard to form an alloy or intermetallic compound with the metal constituting the conductive layer and has a low solid solubility to the conductive layer.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: January 1, 2002
    Assignee: Fujitsu Ltd.
    Inventors: Shin'ya Fukuta, Hiroyasu Kawano, Hideki Harada
  • Publication number: 20010054871
    Abstract: A plasma display panel includes a dielectric layer in which a filler for enhancing reflectance is dispersed. To increase luminescence efficiency, the filler consists of flakes oriented in parallel to the surface of the dielectric layer.
    Type: Application
    Filed: March 28, 2001
    Publication date: December 27, 2001
    Inventors: Shinji Tadaki, Noriyuki Awaji, Fumihiro Namiki, Katsuya Irie, Hideki Harada, Tadayoshi Kosaka
  • Patent number: 6283438
    Abstract: A shock absorbing holder for holding a device vulnerable to an effect by shock so as to wrap it up and protect it against shock. The shock absorbing holder includes a frame body structured smaller than an outer shape of the device, a holding portion having a shape similar to the outer shape of the device defined by inner wall surfaces of the frame body, and protruding portions provided on outer surface walls of the frame body. With the frame body extended, the device is accommodated in the holding portion, being intimately contacted to the inner wall surfaces of the frame body. When shock is imported from outside, the protruding portions are deformed to absorb the shock, protecting the accommodated device from the shock.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: September 4, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Shimada, Hideki Harada, Masayuki Nakayama, Mitsuaki Karumai, Takeshi Mori, Yoshihiro Fukukawa
  • Patent number: 6218318
    Abstract: A semiconductor device includes a porous interlayer insulation film including therein a stacking of SiO2 particles having a diameter in the range between about 5 nm and about 50 nm and stacked so as to form a void between adjacent particles, wherein the interlayer insulation film has a porosity in the range between about 13% and about 42%.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Ohkura, Hideki Harada
  • Patent number: 6191530
    Abstract: An electrode for a display device, including a laminate of an underlying layer, a conductive layer and a protective layer formed on a substrate in this order from the substrate side in such a manner that at least the conductive layer is completely covered by the protective layer, the underlying layer and the protective layer being composed of a metal which is hard to form an alloy or intermetallic compound with the metal constituting the conductive layer and has a low solid solubility to the conductive layer.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: February 20, 2001
    Assignee: Fujitsu Limited
    Inventors: Shin'ya Fukuta, Hiroyasu Kawano, Hideki Harada
  • Patent number: 6099992
    Abstract: A reticle is designed with a method including a step of generating first dummy patterns with intervals from main patterns. Each of the first dummy patterns are divided into a plurality of spaced apart second dummy patterns and then each of the second dummy patterns are measured to find third dummy patterns having widths and areas below smallest allowable values. The third dummy patterns are then respectively connected to second dummy patterns which are adjacent to the third dummy patters by generating a connecting dummy pattern. Selective non-connected third dummy patterns are removed. The first dummy patterns are divided into a plurality of second dummy patterns by vertical and horizontal strip lines crossing the first dummy patterns.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: August 8, 2000
    Assignee: Fujitsu Limited
    Inventors: Takushi Motoyama, Hideki Harada, Takayuki Tsuru
  • Patent number: 5976618
    Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: November 2, 1999
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada
  • Patent number: 5976703
    Abstract: A material and a method for planarizing an uneven surface of a substrate, such as those used for making wiring boards and electronic devices and having broad patterns on their surfaces, are provided. The material is a polysilphenylenesiloxane or a copolymer of polysilphenylenesiloxane with an organosiloxane, and is applied to an uneven surface of a substrate, and then heated to be reflowed to thereby be formed into a planarized film or layer. The material allows a substrate containing wiring having a width of up to several hundred micrometers to be planarized.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shyun-ichi Fukuyama, Michiko Katayama, Joe Yamaguchi, Hideki Harada, Yoshiyuki Ohkura
  • Patent number: 5770260
    Abstract: A process capable of forming an inorganic film which can be used at a relatively large thickness equivalent to, or greater than, the thickness of an organic SOG, without being subjected to oxidation by O.sub.2 plasma treatment used in a fabrication process of a semiconductor device. Polysilazane is first coated on a base, and the resulting polysilazane film is converted to a silicon dioxide film.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 23, 1998
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Shun-ichi Fukuyama, Daitei Shin, Yuki Komatsu, Hideki Harada, Yoshihiro Nakata, Michiko Kobayashi, Yoshiyuki Okura
  • Patent number: 5691237
    Abstract: A semiconductor substrate 11 having concavities and convexities in the upper surface, and silica particles (granular insulators) 15 provided in the concavities to planarize the entire upper surface of the semiconductor substrate 11 are included. First, the silica particles 15 are laid over an upper surface of a semiconductor substrate 11 to provide the granular insulators 15 in cavities in the upper surface of the semiconductor substrate 11, and the silica particles 15 provided on convexities on the upper surface of the semiconductor substrate 11 are removed, whereby the concavities 11 are buried with the silica particles 15 so as to improve global planarizarion.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: November 25, 1997
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Ohkura, Hideki Harada, Tadasi Oshima
  • Patent number: 5448111
    Abstract: A semiconductor substrate 11 having concavities and convexities in the upper surface, and silica particles (granular insulators) 15 provided in the concavities to planarize the entire upper surface of the semiconductor substrate 11 are included. First, the silica particles 15 are laid over an upper surface of a semiconductor substrate 11 to provide the granular insulators 15 in cavities in the upper surface of the semiconductor substrate 11, and the silica particles 15 provided on convexities on the upper surface of the semiconductor substrate 11 are removed, whereby the concavities 11 are buried with the silica particles 15 so as to improve global planarizarion.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: September 5, 1995
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Ohkura, Hideki Harada
  • Patent number: 5310720
    Abstract: A thick planarization layer of silicon dioxide that is heat resistant is provided by coating a polysilazane layer over a substrate having steps and firing the polysilazane layer in an oxygen-containing atmosphere to convert the polysilazane to silicon dioxide. The temperature of this conversion may be as low as 400.degree. to 450.degree. C. while a higher firing or curing temperature is preferable to obtain a more densified oxide layer.
    Type: Grant
    Filed: February 24, 1993
    Date of Patent: May 10, 1994
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Daitei Shin, Hideki Harada
  • Patent number: 5292389
    Abstract: A process for producing a nonwoven fabric having the steps of: bonding polypropylene long-fibers constituting main fibers of the web to one another to produce a raw nonwoven fabric; and uniaxially drawing the raw nonwoven fabric at certain draw temperatures and draw magnifications to produce a final nonwoven fabric.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: March 8, 1994
    Assignee: Idemitsu Petrochemical Co., Ltd.
    Inventors: Issei Tsuji, Hideki Harada, Masato Doi
  • Patent number: 4715178
    Abstract: An improved exhaust port assembly, for an internal combustion engine comprises a port pipe made of heat resistance steel covered by a fibrous ceramic sheet which is covered by an aluminum foil to prevent molten aluminum from penetrating the fibrous ceramic sheet when aluminum casting.
    Type: Grant
    Filed: August 1, 1984
    Date of Patent: December 29, 1987
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yasuo Tsukuda, Hisao Hara, Hideki Harada, Yasuo Iizuka
  • Patent number: 4266328
    Abstract: A core assembly for magnetizing a columnar permanent magnet, especially a columnar ceramic permanent magnet and a developing roll magnetized by the core assembly, adapted for use in an electrostatic developing apparatus of magnetic-brush developing type. The magnetizing iron core assembly has a specific arrangement of magnetic poles and magnetizing coil windings for providing a specific pattern of magnetic flux distribution which would provide the most efficient development.
    Type: Grant
    Filed: May 10, 1979
    Date of Patent: May 12, 1981
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hideki Harada, Keitaro Yamashita, Katsunobu Yamamoto
  • Patent number: 4187330
    Abstract: A method for developing an electrostatic latent image and an apparatus therefor, in which a magnetic toner layer is formed on an arcuate face formed from an insulator, and an electrostatic latent image carrying medium is supported such that its electrostatic latent image surface contacts lightly with a part of said magnetic toner layer.
    Type: Grant
    Filed: January 25, 1977
    Date of Patent: February 5, 1980
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hideki Harada, Keitarou Yamashita