Abstract: A variable resistance memory device includes a first electrode on a substrate, a variable resistance pattern on the first electrode, a second electrode on the variable resistance pattern, a selection pattern structure on the second electrode, and a third electrode on the selection pattern structure. The selection pattern structure may include a first leakage current prevention pattern and a selection pattern sequentially stacked, and the first leakage current pattern may include a two-dimensional transition metal dichalcogenide (TMDC) material.

Abstract: A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

Abstract: A variable resistance memory device includes a first electrode on a substrate, a variable resistance pattern on the first electrode, a second electrode on the variable resistance pattern, a selection pattern structure on the second electrode, and a third electrode on the selection pattern structure. The selection pattern structure may include a first leakage current prevention pattern and a selection pattern sequentially stacked, and the first leakage current pattern may include a two-dimensional transition metal dichalcogenide (TMDC) material.

Abstract: A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Abstract: A variable resistance memory device includes a pattern of one or more first conductive lines, a pattern of one or more second conductive lines, and a memory structure between the first and second conductive lines. The pattern of first conductive lines extends in a first direction on a substrate, and the first conductive lines extend in a second direction crossing the first direction. The pattern of second conductive lines extends in the second direction on the first conductive lines, and the second conductive lines extend in the first direction. The memory structure vertically overlaps a first conductive line and a second conductive line. The memory structure includes an electrode structure, an insulation pattern on a central upper surface of the electrode structure, and a variable resistance pattern on an edge upper surface of the electrode structure. The variable resistance pattern at least partially covers a sidewall of the insulation pattern.

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

Abstract: A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below, [GeASeBTeC](1-U)[X]U??(1) where 0.20?A?0.40, 0.40?B?0.70, 0.05?C?0.25, A+B+C=1, 0.0?U?0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S).

Abstract: A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U??(1) (where 0.05?X?0.1, 0.15?Y?0.25, 0.7?Z?0.8, X+Y+Z=1, 0.45?a?0.6, and 0.08?U?0.2).

Abstract: A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

Abstract: A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below, [GeASeBTeC](1-U)[X]U??(1) where 0.20?A?0.40, 0.40?B?0.70, 0.05?C?0.25, A+B+C=1, 0.0?U?0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S).

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.

Abstract: Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.