Abstract: The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer.

Abstract: Provided are a system and method of determining pulse properties of a semiconductor device. An embodiment of the system includes at least one pair of first and second probes electrically contacting terminals of the semiconductor resistance device, a pulse generator connected to the first probe and outputting pulse signals, an oscilloscope having at least one pair of first and second channels, wherein the pulse electric signal is supplied to the first channel and the first probe and the second channel is connected to the second probe. The oscilloscope calculates a pulse current flowing in terminals of the semiconductor resistance device using the second channel and determines a dynamic resistance of the semiconductor resistance device using the first and second channels.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

Abstract: An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A phase changeable memory element is formed by conformally forming a phase changeable material film in a contact hole on a substrate so as to create a void in the phase changeable material film in the contact hole. The void is at least partially closed by impinging a laser beam on the phase changeable material film sufficiently to reflow the phase changeable material film in the void.

Abstract: In a method of forming a conductive line for a semiconductor device using a carbon nanotube and a semiconductor device manufactured using the method, the method includes activating a surface of an electrode of the semiconductor device using surface pretreatment to create an activated surface of the electrode, forming an insulating layer on the activated surface of the electrode, and forming a contact hole through the insulating layer to expose a portion of the activated surface of the electrode, and supplying a carbon-containing gas onto the activated surface of the electrode through the contact hole to grow a carbon nanotube, which forms the conductive line, on the activated surface of the electrode. Alternatively, the activation step of the surface of the electrode may be replaced with a formation of a catalytic metal layer on the surface of the electrode.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

Abstract: An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided.

Abstract: A method of forming a capacitor of a semiconductor memory device is provided. In the capacitor formation, a insulating layer is deposited over a semiconductor substrate, and patterned into a insulating pattern with a hole that exposes the semiconductor substrate. Next, a seed layer for use in forming a lower electrode is formed over the surface of the exposed semiconductor substrate, the inner walls of the hole, and the insulating pattern, and a plating mask layer is selectively formed on the seed layer deposited on the insulating pattern, and on a portion of the seed layer from the upper edges of the insulating pattern deposited along the sidewalls of the hole to a predetermined depth, such that the seed layer formed in the hole is exposed. The plating mask layer is formed by a physical vapor deposition (PVD) or a plasma chemical vapor deposition (CVD) method.

Abstract: A capacitor having an electrode formed by electroplating, and a manufacturing method thereof are disclosed. According to an embodiment of the invention, a conductive film is formed on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film formed around the conductive plug. Then, a non-conductive pattern exposing a part of the conductive film on the conductive plug is formed on the conductive film, and a lower electrode, which is formed of a platinum (Pt) group metal, is formed on the conductive film by electroplating. In addition, the lower electrode can have a rectangular, T-shaped, reverse trapezoid or barrel-shaped cross-section. Electroplating can similarly form an upper electrode of the capacitor.

Abstract: A method of forming a capacitor of a semiconductor memory device is provided. In the capacitor formation, a insulating layer is deposited over a semiconductor substrate, and patterned into a insulating pattern with a hole that exposes the semiconductor substrate. Next, a seed layer for use in forming a lower electrode is formed over the surface of the exposed semiconductor substrate, the inner walls of the hole, and the insulating pattern, and a plating mask layer is selectively formed on the seed layer deposited on the insulating pattern, and on a portion of the seed layer from the upper edges of the insulating pattern deposited along the sidewalls of the hole to a predetermined depth, such that the seed layer formed in the hole is exposed. The plating mask layer is formed by a physical vapor deposition (PVD) or a plasma chemical vapor deposition (CVD) method.

Abstract: A capacitor having an electrode formed by electroplating, and a manufacturing method thereof are disclosed. According to an embodiment of the invention, a conductive film is formed on a conductive plug connected to an active region of a semiconductor substrate, and on an interlayer dielectric (ILD) film formed around the conductive plug. Then, a non-conductive pattern exposing a part of the conductive film on the conductive plug is formed on the conductive film, and a lower electrode, which is formed of a platinum (Pt) group metal, is formed on the conductive film by electroplating. In addition, the lower electrode can have a rectangular, T-shaped, reverse trapezoid or barrel-shaped cross-section.

Abstract: A method of fabricating a self-aligned stacked capacitor is provided, in which buried contacts and storage nodes are simultaneously formed by electroplating. In this method, a semiconductor substrate having exposed conductive areas is prepared for, and an interlayer insulative layer having buried contact holes that expose the conductive areas, is formed over the semiconductor substrate. A lower conductive seed layer is then formed over the entire surface of the innerwalls of the buried contact holes and the upper surface of the interlayer insulative layer. Non-conductor patterns having storage node holes that expose the buried contact holes, are then formed over the lower conductive seed layer on the upper surface of the interlayer insulative layer. A buried contact that fills the buried contact hole, and a lower electrode that fills the storage node hole, are then simultaneously formed by electroplating.