Abstract: In one embodiment of the present invention, a video signal processing method is disclosed wherein video correction data is read from a ROM and written into an LUT, and the video correction data written in the LUT is used to perform data correction of an externally inputted video signal. The video correction data written in the LUT is updated during the horizontal blanking interval of the video signal.

Abstract: In one embodiment of the present invention, a liquid crystal panel driving device for AC-driving a liquid crystal panel with first and second polarities includes an output tone generating section for generating an output tone corresponding to an input tone. With respect to the same input tone, the output tone generating section generates a first output tone when driving the liquid crystal panel with a first polarity, and generates a second output tone when driving the liquid crystal panel with a second polarity. The first and second output tones are determined based on a characteristic of the input tone and the center of amplitude of a voltage to be outputted in response to the input tone in AC driving. This allows providing a liquid crystal panel driving device capable of easily performing ? correction with respect to each liquid crystal panel.

Abstract: In one embodiment of the present invention, in an even-numbered signal line group, the arrangement sequence of the first and second signal lines is reversed between in a display area and in a non-display area, and the same goes for the arrangement sequence of the third and fourth signal lines. The ends of the first to sixteenth signal lines in the non-display area are connected to the first to sixteenth individual drivers, respectively. An odd-numbered individual driver and an even-numbered individual driver each output a corresponding one of drive signals of opposite polarity. Thus, the polarities of subpixels of the same color arranged in a first direction D1 (horizontal direction) differ between the subpixels connected to the odd-numbered signal line group and the subpixels connected to the even-numbered signal line group. That is, all of the subpixels having the same color arranged in the horizontal direction do not have the same polarity. This helps reduce a horizontal shadow.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate S× which is a change quantity per unit time, and by desirably setting the change rate S×, a change rate S×1 in the vicinity of an input-side end of the scanning signal line and a change rate S×N in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In a display device of the present invention, during a period until the start of outputting display data from a source driver, a timing control ASIC generates a gate start pulse signal GSP and a first pulse CK1 of a gate clock signal GCK, with reference to the timing of inputting a data enable signal ENAB. The signals having been generated are supplied to the gate driver, so that a dummy line G0 is driven.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sxl in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In a display device of the present invention, during a period until the start of outputting display data from a source driver, a timing control ASIC generates a gate start pulse signal GSP and a first pulse CK1 of a gate clock signal GCK, with reference to the timing of inputting a data enable signal ENAB. The signals having been generated are supplied to the gate driver, so that a dummy line G0 is driven.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sxl in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In a display device of the present invention, during a period until the start of outputting display data from a source driver, a timing control ASIC generates a gate start pulse signal GSP and a first pulse CK1 of a gate clock signal GCK, with reference to the timing of inputting a data enable signal ENAB. The signals having been generated are supplied to the gate driver, so that a dummy line G0 is driven.

Abstract: A plurality of signal input-output sections are connected with each other in a cascade manner. In each signal input-output section, an input latch circuit divides a data signal into 2 channels in accordance with the first clock signal, and an output latch circuit returns the data signal that has been divided into 2 channels to 1 channel in accordance with the second clock signal so as to be outputted to the signal input-output section of the next stage. The inputted first basic clock is outputted to the signal input-output section of the next stage as the second basic clock, and the inputted second basic clock is outputted to the signal input-output section of the next stage as the first basic clock. This allows to ensure the data sampling margin even when the data signal should be transferred at a faster speed, and also allows to suppress the problem of the EMI.

Abstract: A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: A plurality of signal input-output sections are connected with each other in a cascade manner. In each signal input-output section, an input latch circuit divides a data signal into 2 channels in accordance with the first clock signal, and an output latch circuit returns the data signal that has been divided into 2 channels to 1 channel in accordance with the second clock signal so as to be outputted to the signal input-output section of the next stage. The inputted first basic clock is outputted to the signal input-output section of the next stage as the second basic clock, and the inputted second basic clock is outputted to the signal input-output section of the next stage as the first basic clock. This allows to ensure the data sampling margin even when the data signal should be transferred at a faster speed, and also allows to suppress the problem of the EMI.

Abstract: A level converting circuit converts the level of an input signal to a positive or a negative level according to a power source voltage for supplying a voltage of a reference level for the input signal. In the level converting circuit, a first transistor has a source supplied with a first voltage, and a drain supplied with a second voltage via a loading circuit. Conduction and cutoff of the first transistor is determined on the basis of the signal level of an input signal supplied via a signal input terminal. The drain voltage is supplied as a signal to an output circuit. The output circuit is supplied via a power source terminal with a third voltage, and via another power source terminal with a fourth voltage. Conduction and cutoff of a transistor of the output circuit is determined on the basis of the signal level of the signal supplied to the output circuit, and the third and fourth voltages are selectively outputted as an output signal of the output circuit.

Abstract: A production/purchase management processing system is provided which includes a master production schedule which describes a production planning of each of a plurality of kinds of products independently for each period. A product construction/item master is provided in the system for describing information related to parts which form the product for each of the products. A stock/remaining order information source of the system describes stock quantity and remaining orders for the items which represent the product or the part. A production planning processor reads the contents of the master production schedule, the product construction/item master and the stock/remaining order information source and outputs a purchase planning order and a production planning order which are generated based on the read contents.