Patents by Inventor Hideki Shibata

Hideki Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8133813
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 8130070
    Abstract: A multiple fuse device for a vehicle includes a circuit board with a battery-side bus bar portion and an alternator-side bus bar portion connected together by a temporary joint portion at a position apart from a fusing portion that provides charging current protection. An insulator housing is placed over the circuit board but the temporary joint portion is left uncovered by the insulator housing. A temporary joint portion is then at least partially removed. This partial removal may leave behind two temporary joint portion remnants, one on the battery-side bus bar portion, and one on the alternator-side bus bar portion. The temporary joint portion thus enhances the strength of the circuit board while the fuse device is being manufactured, which prevents the fusing portion from being accidentally deformed or broken during the device's assembly.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 6, 2012
    Assignee: Pacific Engineering Corporation
    Inventor: Hideki Shibata
  • Patent number: 8110421
    Abstract: A method for manufacturing a light emitting device includes: forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate; forming a dielectric film on a second surface side opposite to the first surface of the multilayer body, the dielectric film having a first and second openings on a p-side electrode and an n-side electrode provided on the second surface; forming a seed metal on the dielectric film and an exposed surface of the first and second openings; forming a p-side metal interconnect layer and an n-side metal interconnect layer on the seed metal; separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal, which is provided between the p-side metal interconnect layer and the n-side metal interconnect layer; and forming a resin in a space from which the seed metal is removed.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Sugizaki, Hideki Shibata, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu, Akihiro Kojima
  • Publication number: 20110297980
    Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting chip and a fluorescent material layer. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The fluorescent material layer is provided on the first major surface and has a larger planer size than the light emitting chip.
    Type: Application
    Filed: September 21, 2010
    Publication date: December 8, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu
  • Publication number: 20110297994
    Abstract: According to one embodiment, a semiconductor light emitting device includes a plurality of semiconductor layers, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar and a resin layer, and is mounted in a bent state on a curved surface. The plurality of semiconductor layers includes a first main surface, a second main surface opposite to the first main surface, and a light emitting layer, the plurality of semiconductor layers being separated from one another. A material is provided between the plurality of the semiconductor layers separated from one another. The member has a higher flexibility than the semiconductor layers being.
    Type: Application
    Filed: September 16, 2010
    Publication date: December 8, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu
  • Publication number: 20110291149
    Abstract: According to one embodiment, a light emitting device includes a light emitting chip, an external terminal made of a metal material, and a circuit board. The light emitting chip is mounted on the circuit board via the external terminal. The light emitting chip includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar and a resin layer. The circuit board includes an interconnection bonded to the first metal pillar and the second metal pillar via the external terminal, and a heat radiation material provided on an opposite side of the interconnection and connected to the interconnection.
    Type: Application
    Filed: September 20, 2010
    Publication date: December 1, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu
  • Publication number: 20110259133
    Abstract: A speed change gear includes: a housing that has internal gears having different inside diameters; and a plurality of change gear units that are respectively in mesh with the plurality of internal gears and that change the speed of rotation from an input shaft to an output shaft. Each of the change gear units includes a rotating member that has one of a pin protruding in a direction along an input/output axis and an insertion hole; an eccentric member that centers on an eccentric axis that is eccentric with respect to the input/output axis; and an oscillating member that oscillatingly rotates as the eccentric member rotates about the input/output axis.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 27, 2011
    Applicant: JTEKT Corporation
    Inventors: Tsune KOBAYASHI, Hideki Shibata
  • Publication number: 20110233586
    Abstract: According to one embodiment, a light emitting device includes a stacked body, a p-side and n-side electrodes, an insulating film, a p-side extraction electrode, an n-side extraction electrode, a resin layer and a phosphor layer. The stacked body has a first and a second surface opposite to each other and includes a light emitting layer. A p-side and an n-side electrode are provided on the second surface. An insulating film has openings to which the p-side and n-side electrodes are exposed. A p-side extraction electrode includes a p-side seed metal and a p-side metal wiring layer. An n-side extraction electrode includes an n-side seed metal and an n-side metal wiring layer. A resin layer is filled around the p-side and n-side extraction electrodes, and a phosphor layer is provided on a side of the first surface. Emission light from the light emitting layer is emitted through the first surface.
    Type: Application
    Filed: July 8, 2010
    Publication date: September 29, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki, Hideki Shibata, Hideo Tamura, Tetsuro Komatsu, Masayuki Ishikawa
  • Publication number: 20110233585
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a first metal pillar, a second metal pillar, a resin, and a fluorescent layer. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode and the second electrode are provided on the second major surface of the semiconductor layer. The fluorescent layer faces to the first major surface of the semiconductor layer and includes a plurality of kinds of fluorescent materials having different peak wavelengths of emission light.
    Type: Application
    Filed: June 17, 2010
    Publication date: September 29, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki, Hideki Shibata, Hideo Tamura, Tetsuro Komatsu, Masayuki Ishikawa
  • Publication number: 20110189849
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7943517
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20110095859
    Abstract: A multiple fuse device for a vehicle includes a circuit board with a battery-side bus bar portion and an alternator-side bus bar portion connected together by a temporary joint portion at a position apart from a fusing portion that provides charging current protection. An insulator housing is placed over the circuit board but the temporary joint portion is left uncovered by the insulator housing. A temporary joint portion is then at least partially removed. This partial removal may leave behind two temporary joint portion remnants, one on the battery-side bus bar portion, and one on the alternator-side bus bar portion. The temporary joint portion thus enhances the strength of the circuit board while the fuse device is being manufactured, which prevents the fusing portion from being accidentally deformed or broken during the device's assembly.
    Type: Application
    Filed: March 17, 2008
    Publication date: April 28, 2011
    Inventor: Hideki Shibata
  • Publication number: 20110027985
    Abstract: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 3, 2011
    Inventors: Kazumichi TSUMURA, Hideki SHIBATA, Masaki YAMADA
  • Patent number: 7855141
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
  • Patent number: 7795733
    Abstract: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Hideki Shibata, Masaki Yamada
  • Publication number: 20100207274
    Abstract: A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 19, 2010
    Inventors: Yumi HAYASHI, Hideki Shibata
  • Patent number: 7768127
    Abstract: The semiconductor device includes a semiconductor substrate, and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. All of the wiring layers are made of a same basis metal, at least one of the wiring layers contains an additive element, and a concentration of the additive element is lower on an upper layer side than that on a lower layer side.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Yamada, Hideki Shibata
  • Patent number: 7750473
    Abstract: Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takamasa Usui, Hideki Shibata, Tadashi Murofushi, Masakazu Jimbo, Hiroshi Hirayama
  • Patent number: 7745326
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 29, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
  • Publication number: 20100148198
    Abstract: A method for manufacturing a light emitting device includes: forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate; forming a dielectric film on a second surface side opposite to the first surface of the multilayer body, the dielectric film having a first and second openings on a p-side electrode and an n-side electrode provided on the second surface; forming a seed metal on the dielectric film and an exposed surface of the first and second openings; forming a p-side metal interconnect layer and an n-side metal interconnect layer on the seed metal; separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal, which is provided between the p-side metal interconnect layer and the n-side metal interconnect layer; and forming a resin in a space from which the seed metal is removed.
    Type: Application
    Filed: July 20, 2009
    Publication date: June 17, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki SUGIZAKI, Hideki Shibata, Masayuki Ishikawa, Hideo Tamura, Tetsuro Komatsu, Akihiro Kojima