Abstract: A semiconductor device which comprises a wiring structure capable of reducing stress concentration at a boundary between a wiring and a low dielectric constant insulator even when the low dielectric constant insulator is used as an interlevel or interwiring insulator in a multilevel wiring, suppressing peeling-off of the insulator and having increased heat radiation efficiency is provided by comprising an insulator formed on a semiconductor substrate, a wiring formed in the insulator, and a network dummy formed in the insulator and disposed to be apart from the wiring.

Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Abstract: The semiconductor device includes a semiconductor substrate and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. The resistance value of a wiring layer located on an upper side of an adjacent pair of wiring layers is lower than or equal to that of a wiring layer located on a lower side of the adjacent pair, and the resistance value of the lowermost layer is higher than that of the uppermost layer. The specific inductive capacity of an insulating layer located on an upper side of an adjacent pair of insulating layers is higher than or equal to that of an insulating layer located on a lower side of the adjacent pair, and the specific inductive capacity of the lowermost layer is lower than that of the uppermost layer.

Abstract: A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

Abstract: The semiconductor device includes a semiconductor substrate and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. The resistance value of a wiring layer located on an upper side of an adjacent pair of wiring layers is lower than or equal to that of a wiring layer located on a lower side of the adjacent pair, and the resistance value of the lowermost layer is higher than that of the uppermost layer. The specific inductive capacity of an insulating layer located on an upper side of an adjacent pair of insulating layers is higher than or equal to that of an insulating layer located on a lower side of the adjacent pair, and the specific inductive capacity of the lowermost layer is lower than that of the uppermost layer.

Abstract: A semiconductor device has an active element structure formed on a semiconductor substrate. The active element has a connection region formed on a surface of the semiconductor substrate. An insulating film is formed on the semiconductor substrate. A connection hole is formed in the insulating film, and has a bottom connected with the connection region. An interconnect trench is formed in the insulating film, and has a bottom connected with the connection region. A first conductive film is filled in a first region ranging from the connection region in the connection hole to a first height, and is composed of an alloy containing CoW or NiW. A second conductive film is formed in the interconnect trench, and is electrically connected with the first conductive film.

Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.

Abstract: This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation l 0 = L C + R 2 + 8 ⁢ π 2 ⁢ f

Abstract: A semiconductor device having a multilayer structure is disclosed, which comprises at least two wiring layers, and a via contact formed between the at least two layers and made of the same metal wiring material as the metal wiring material of the at least two wiring layers, wherein the metal wiring material of the via contact contains an additive which is not contained in the metal wiring materials of the at least two wiring layers.

Abstract: There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation 1 l 0 = L C + R 2 + 8 ⁢   ⁢ π 2 ⁢ f 0 2 ⁢ L 2 4 ⁢   ⁢ π 2 ⁢ f 0 2 ⁢ C 2 R 2 + 4 ⁢ π 2 ⁢ f 0 2 ⁢ L 2