Patents by Inventor Hideki Shibata

Hideki Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090280642
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Application
    Filed: July 13, 2009
    Publication date: November 12, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki SHIMOOKA, Hideki SHIBATA, Hideshi MYAJIMA, Kazuhiro TOMIOKA
  • Publication number: 20090275194
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Application
    Filed: July 13, 2009
    Publication date: November 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
  • Patent number: 7589014
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
  • Publication number: 20090132100
    Abstract: An aircraft (1) and a terrestrial station (40) for communicating with each other are provided. An airframe and a payload device of an aircraft is controlled from the terrestrial station. The aircraft (1) transmits data concerning a situation of the airframe, a situation of a flight, and a situation of the payload device to the terrestrial station (40). The terrestrial station (40) includes one monitor screen (56) for simultaneously displaying all the data transmitted from the aircraft and an operation panel.
    Type: Application
    Filed: March 20, 2006
    Publication date: May 21, 2009
    Inventor: Hideki Shibata
  • Publication number: 20090115636
    Abstract: The present invention provides a fuselage information display panel of an aircraft for displaying a display section arranged vertically and horizontally provided for each of a plurality of different information items. The display section changes color according to the contents of the displayed information (e.g., whether the displayed information identifies normal or abnormal operation).
    Type: Application
    Filed: March 29, 2006
    Publication date: May 7, 2009
    Applicant: Yamaha Hatsudoki Kabushiki Kaisha
    Inventor: Hideki Shibata
  • Patent number: 7485915
    Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
  • Publication number: 20080203573
    Abstract: Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.
    Type: Application
    Filed: December 19, 2007
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa Usui, Hideki Shibata, Tadashi Murofushi, Masakazu Jimbo, Hiroshi Hirayama
  • Publication number: 20080057704
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: October 23, 2007
    Publication date: March 6, 2008
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7304384
    Abstract: A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: December 4, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20070093052
    Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.
    Type: Application
    Filed: November 30, 2006
    Publication date: April 26, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
  • Publication number: 20070035032
    Abstract: A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.
    Type: Application
    Filed: April 7, 2006
    Publication date: February 15, 2007
    Inventors: Kazumichi Tsumura, Hideki Shibata, Masaki Yamada
  • Publication number: 20070037374
    Abstract: A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof.
    Type: Application
    Filed: November 17, 2005
    Publication date: February 15, 2007
    Inventors: Yumi Hayashi, Hideki Shibata
  • Publication number: 20070012973
    Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.
    Type: Application
    Filed: May 5, 2006
    Publication date: January 18, 2007
    Inventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
  • Publication number: 20070004049
    Abstract: A semiconductor device includes a gate insulating film which at least includes a first insulating film formed on the main surface of a semiconductor substrate and a first ferroelectric film formed on the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a gate electrode formed on the gate insulating film and containing one of Cu and a material containing Cu as a main component, and source and drain regions separately formed in the semiconductor substrate to sandwich the gate electrode.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 4, 2007
    Inventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
  • Publication number: 20070001307
    Abstract: A semiconductor device includes a guard ring formed in an inter-level insulating film on a semiconductor substrate to surround an element forming region on the semiconductor substrate and containing Cu as a main component. And the device further includes a first barrier film formed on an interface between the inter-level insulating film and the guard ring and containing a compound of a preset metal element and a constituent element of the inter-level insulating film as a main component.
    Type: Application
    Filed: May 25, 2006
    Publication date: January 4, 2007
    Inventors: Takamasa Usui, Hayato Nasu, Hideki Shibata
  • Publication number: 20060244144
    Abstract: The semiconductor device includes a semiconductor substrate, and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. All of the wiring layers are made of a same basis metal, at least one of the wiring layers contains an additive element, and a concentration of the additive element is lower on an upper layer side than that on a lower layer side.
    Type: Application
    Filed: October 17, 2005
    Publication date: November 2, 2006
    Inventors: Masaki Yamada, Hideki Shibata
  • Patent number: 7115999
    Abstract: A semiconductor device has an active element structure formed on a semiconductor substrate. The active element has a connection region formed on a surface of the semiconductor substrate. An insulating film is formed on the semiconductor substrate. A connection hole is formed in the insulating film, and has a bottom connected with the connection region. An interconnect trench is formed in the insulating film, and has a bottom connected with the connection region. A first conductive film is filled in a first region ranging from the connection region in the connection hole to a first height, and is composed of an alloy containing CoW or NiW. A second conductive film is formed in the interconnect trench, and is electrically connected with the first conductive film.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Hideki Shibata
  • Patent number: D549058
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: August 21, 2007
    Assignee: Pacific Engineering Corp.
    Inventors: Hideki Shibata, Eiji Murakami
  • Patent number: D551174
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: September 18, 2007
    Assignees: Pacific Engineering Corp., Sumitomo Wiring Systems, Ltd.
    Inventors: Manabu Ohta, Hideki Shibata, Katsuya Ito
  • Patent number: D560172
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: January 22, 2008
    Assignees: Pacific Engineering Corp., Sumitomo Wiring Systems, Ltd.
    Inventors: Manabu Ohta, Hideki Shibata, Katsuya Ito