Abstract: A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE for the insulating film is greater than that for the stopper film. The stopper film and insulating film are formed on the insulating film. A pattern of the contact hole is formed in the stopper film. A wiring pattern is formed on the resist film. The insulating films are etched by RIE with the resist film and stopper film used as masks. Thus, a groove for formation of wiring and a contact hole for formation of a contact plug are simultaneously formed in a self-alignment manner.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.

Abstract: A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE for the insulating film is greater than that for the stopper film. The stopper film and insulating film are formed on the insulating film. A pattern of the contact hole is formed in the stopper film. A wiring pattern is formed on the resist film. The insulating films are etched by RIE with the resist film and stopper film used as masks. Thus, a groove for formation of wiring and a contact hole for formation of a contact plug are simultaneously formed in a self-alignment manner.

Abstract: A semiconductor device has a metal silicide on silicon conductor formed using a salicide process. The metal silicide layer of the conductor includes boron which improves the morphology and conductivity of the metal silicide layer. Implanting boron into the metal silicide layer or the metal to be silicided prevents the metal silicide from aggregating during a subsequent annealing or other heating process. This process allows narrower conductors to be formed without undesirable increases in the resistance of the metal silicide layer. The boron incorporating salicide process is compatible with CMOS processes.

Abstract: A method of manufacturing semiconductor devices yielding devices having impurity regions that are more shallow and exhibit less lateral diffusion than devices manufactured in accordance with prior art techniques. First, arsenic is introduced into a substrate. After the introduction of arsenic, phosphorus is introduced to the same portion of the substrate. The introductions of arsenic and phosphorus may be accomplished using diffusion or ion implantation techniques.

Abstract: The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer.

Abstract: A first insulating layer is formed on the major surface of a semiconductor substrate, and a first-level metal wiring layer is formed on the first insulating layer. A refractory metal layer is selectively grown on that side portion (or those side and upper portions) of the first-level metal wiring layer which is (or are) located in the vicinity of a contact formation region of the first-level metal wiring layer. A second insulating layer is formed on the resultant structure, and then a through hole is formed by the RIE method in the first-level metal wiring layer in the contact formation region. The first-level metal wiring layer, or the first-level metal wiring layer and part of the refractory metal layer are exposed through the through hole. A second-level metal wiring layer is formed such that it fills the through hole, extends on part of the second insulating layer, and is electrically connected to the first-level metal wiring layer.

Abstract: A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a via hole. Filling a wiring conductor in the via hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.

Abstract: A semiconductor integrated circuit device and its manufacturing method are disclosed, the method comprising the steps of forming, over a semiconductor substrate, a first interconnection layer which involves a step-like surface, forming, over a first interconnection layer, an insulating layer and planarizing the surface of the second insulating layer, providing a plurality of via holes of different depths in the insulating layer reaching the first interconnection layer, subsequent to the step, implanting an impurity ion in the first interconnection layer such that an electronegativity in the first interconnection layer varies in accordance with the depths of the via holes, depositing a metal film in the via holes, and forming a second interconnection layer over the insulating layer so as to be connected to the first interconnection layer by the deposited metal film in the via holes.

Abstract: A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a VIA hole. Filling a wiring conductor in the VIA hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.

Abstract: A semiconductor device comprising a substrate, a first metal wiring layer made of aluminum alloy and formed on the substrate, a conductive film made of doped polysilicon and formed on a selected part of the first metal wiring layer, an inter-layer insulation film made of plasma SiO.sub.2 and formed on the conductive film and the first metal wiring layer, a contact hole formed in the inter-layer insulation film and being larger than the conductive film, and a second metal wiring layer made of aluminum alloy, extending through the contact hole, and connected to the conductive film.

Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact.

Abstract: A semiconductor device comprises a MOSFET of LDD structure, in which the gate electrode structure comprises an oxide film interposed between a poly-Si layer and a refractory metal layer or a metal silicide. The oxide film prevents the metal or metal silicide from being diffused into the gate oxide film during the heating step included in the process of manufacturing the semiconductor device. Also, a side wall spacer is formed of poly-Si to achieve an electrical connection between the poly-Si layer and the layer of the metal having a high melting point or of the metal silicide so as to constitute a part of the gate electrode.

Abstract: A method for manufacturing MOS semiconductor devices comprises the steps of forming a oxidation resistant film on the upper and side surfaces of a gate electrode which is formed on a silicon substrate via an oxide film and whose upper and side surfaces are coated with an insulation oxide film, effecting thermal oxidation with the oxidation resistant film as a mask, removing the oxidation resistant film and the oxide film lying directly under the oxidation resistant film to expose the surface of the substrate, doping impurity into the exposed surface area of the substrate to form impurity regions, forming a silicon layer on the exposed surface of the substrate by a growth process, forming a first refractory metal layer on the entire surface of the structure, forming an insulation film on the first refractory metal layer, selectively removing the insulation film to form a contact hole, forming a second refractory metal layer in the contact hole by a deposition process, removing the insulation film and the first

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer formed on the substrate, a conductive body formed on the first insulating layer, a second insulating layer formed on the first insulating layer and the conductive body and having a contact hole formed at a contact area to reach the conductive body, and a first conductive layer formed on the second insulating layer and the conductive body. The conductive body has a conductive member formed on the first insulating layer in the contact area, and a second conductive layer formed on the first insulating layer and the conductive member.