Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10384567
    Abstract: A vehicle seat includes a seat cushion frame, a slide mechanism, a drive source, and a transmission mechanism configured to receive a driving force from the drive source and to cause the seat cushion frame to move in a front-rear direction. The slide mechanism includes a guide member extending in the front-rear direction and a slide member movable along the guide member relative to the guide member; the seat cushion frame is fixed to one of the guide member and the slide member, and another of the guide member and the slide member is fixed to a floor of a vehicle; and the drive source is fixed to the floor of the vehicle.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: August 20, 2019
    Assignee: TS TECH CO., LTD.
    Inventors: Hajime Yoshida, Koji Onuma, Hideki Usami, Kazuhiro Hayashi
  • Publication number: 20190235787
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Application
    Filed: September 10, 2018
    Publication date: August 1, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA
  • Publication number: 20190216352
    Abstract: Provided is an electrode sheet allowing easy connection of a wiring that is extended, when required, to a measurement position on a living body. The electrode sheet (main sheet (1), auxiliary sheet (10)) includes a sheet-shaped flexible substrate (2, 11), wirings (3, 12) formed on the flexible substrate (2, 11), electrodes (5, 14) formed on the flexible substrate (2, 11) and electrically connected to the wirings (3, 12), and an insulating layer (4, 13) laid on the flexible substrate (2, 11) in such a manner that the wirings (3, 12) are overlaid with the insulating layer (4, 13) while the electrodes (5, 14) are exposed. The electrodes (5, 14) are formed of a conductive material in which conductive particles are dispersed in a thermoplastic resin.
    Type: Application
    Filed: August 17, 2017
    Publication date: July 18, 2019
    Inventors: Tsuyoshi SEKITANI, Takafumi UEMURA, Teppei ARAKI, Shusuke YOSHIMOTO, Masayuki IWASE, Akio YOSHIDA, Hideki SATAKE
  • Patent number: 10355530
    Abstract: A control circuit controls a plurality of conversion switching elements by first drive signals and a plurality of adjustment switching elements by second drive signals. The control circuit is configured to adjust a phase difference which is a delay of the phase of each of the second drive signals to the phase of each of the first drive signals to a set value within a prescribed range to adjust the magnitude of output power. The prescribed range includes at least one of a range of 270 degrees to 360 degrees and a range of 90 degrees to 180 degrees.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: July 16, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yusuke Tanji, Hideki Tamura, Kazumasa Yoshida
  • Patent number: 10347447
    Abstract: A vacuum circuit breaker includes a tank containing an electrical device. An opening corresponds to a terminal of the electrical device. A porcelain tube protruding from the tank is fixed to an opening base, and has a terminal conductor. A first connection conductor in the porcelain tube is connected to the terminal conductor. A second connection conductor is arranged in the porcelain tube. A third connection conductor is arranged between the first and the second connection conductor, has a closed end concave section fitted onto the first connection conductor and is connected to the second connection conductor by a fastener. A contact is disposed between said first connection conductor and the third connection conductor. The third and second connection conductors are made of a solid conductor. A center of the third connection conductor and a center of the second connection conductor are formed with a threaded section.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 9, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideki Miyatake, Masahiro Arioka, Tadahiro Yoshida, Toshihiro Matsunaga, Toru Kimura, Naoki Tanaka
  • Patent number: 10336626
    Abstract: A method for producing a nickel cobalt complex hydroxide includes first crystallization of supplying a solution containing Ni, Co and Mn, a complex ion forming agent and a basic solution separately and simultaneously to one reaction vessel to obtain nickel cobalt complex hydroxide particles, and a second crystallization of, after the first crystallization, further supplying a solution containing nickel, cobalt, and manganese, a solution of a complex ion forming agent, a basic solution, and a solution containing said element M separately and simultaneously to the reaction vessel to crystallize a complex hydroxide particles containing nickel, cobalt, manganese and said element M on the nickel cobalt complex hydroxide particles crystallizing a complex hydroxide particles comprising Ni, Co, Mn and the element Mon the nickel cobalt complex hydroxide particles.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 2, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
  • Publication number: 20190198402
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Inventors: Hideki AONO, Tetsuya YOSHIDA, Makoto OGASAWARA, Shinichi OKAMOTO
  • Patent number: 10328438
    Abstract: A tube rack of a centrifugal separator, in which a bottom rubber portion can be readily mounted and readily replaced, and yet such bottom rubber portion cannot be easily separated. The tube rack includes a holder (14) including a plurality of tube holes (12) each configured to accommodate a tube that is used for a sample and each includes an opening at one end portion of the holder serving as a tube insertion side, and an opening at a bottom portion of the holder that is at the other end. The tube rack includes a bottom rubber portion (15) including a plurality of bottom rubber members (25) each fits in the tube hole (12), and including connecting pieces (24). The tube rack includes a base (13) formed in a cylindrical shape having a bottom configured to accommodate and detachably hold the holder (14) and the bottom rubber portion (15), and to be inserted into a bucket of the centrifugal separator.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: June 25, 2019
    Assignee: KUBOTA MANUFACTURING CORPORATION
    Inventor: Hideki Yoshida
  • Publication number: 20190189344
    Abstract: A multilayer capacitor includes an element assembly, a first external electrode, a second external electrode, and a plurality of internal electrodes which are disposed at the inside of the element assembly. The plurality of internal electrodes include a first internal electrode that is electrically connected to the first external electrode, a second internal electrode that is electrically connected to the second external electrode, and a plurality of third internal electrodes. The plurality of third internal electrodes are electrically connected to each other by a first connection conductor and a second connection conductor, a first capacitance portion is constituted by the first internal electrode and the third internal electrodes, a second capacitance portion is constituted by the second internal electrode and the third internal electrodes, and the first capacitance portion and the second capacitance portion are electrically connected in series.
    Type: Application
    Filed: January 23, 2019
    Publication date: June 20, 2019
    Applicant: TDK CORPORATION
    Inventors: Takeru YOSHIDA, Takuya IMAEDA, Shogo MUROSAWA, Hideki KAMO, Naoto IMAIZUMI, Keiichi TAKIZAWA
  • Publication number: 20190189421
    Abstract: The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from ?1.0 ?m to 1.0 ?m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.
    Type: Application
    Filed: April 6, 2018
    Publication date: June 20, 2019
    Applicant: JX Nippon Mining & Metals Corporation
    Inventors: Taku YOSHIDA, Hideki KURITA
  • Patent number: 10325899
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Publication number: 20190179567
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to he written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Application
    Filed: June 11, 2018
    Publication date: June 13, 2019
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20190179751
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Application
    Filed: June 11, 2018
    Publication date: June 13, 2019
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20190142162
    Abstract: Enabling an overturn preventing device to be installed even when a space between a top surface of an article and a ceiling is narrow. A bracket of an overturn preventing device is mounted to a piece of furniture to be prevented from overturn. The bracket has a lower part supporting a first base of a damper of the overturn preventing device at a position lower than a top surface of the furniture. The overturn preventing device can be easily installed even when a space between the top surface of the furniture and the ceiling is narrow.
    Type: Application
    Filed: February 28, 2017
    Publication date: May 16, 2019
    Applicant: KYB CORPORATION
    Inventors: Hiroki TOKUDA, Takahiro YOSHIDA, Hideki KAWAKAMI, Naoki KUBOTA
  • Publication number: 20190138226
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Application
    Filed: June 11, 2018
    Publication date: May 9, 2019
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20190129862
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Application
    Filed: May 21, 2018
    Publication date: May 2, 2019
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20190129838
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Application
    Filed: May 21, 2018
    Publication date: May 2, 2019
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20190121418
    Abstract: According to one embodiment, a storage includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The storage is supplied with first power from a power supply unit. The controller is configured to change power supplied from the power supply unit from the first power to second power based on a power control command transmitted from a host. The power control command includes a first parameter identifying the storage and a second parameter indicative of the second power.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Naoki Sawai, Hiroshi Murayama, Hiroshi Nishimura, Shinichi Kanno, Hideki Yoshida
  • Publication number: 20190114116
    Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida
  • Publication number: 20190087323
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: March 7, 2018
    Publication date: March 21, 2019
    Inventors: Shinichi Kanno, Hideki Yoshida