Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210325681
    Abstract: A head-mounted display (10) according to the present disclosure, includes: a front block (100) that supports a display unit to be disposed in front of an eye of a user; a rear block (300) that is to be disposed on a back side of a head of the user; and a plurality of elastic bodies (230, 340) that extend along a belt for linking the front block (100) to the rear block (300). Each of the plurality of elastic bodies (230, 240) has one end fixed to the belt and another end fixed to a predetermined position in the rear block (300).
    Type: Application
    Filed: June 26, 2019
    Publication date: October 21, 2021
    Inventors: TAKAAKI YOSHIDA, HIDEKI TAKAHASHI, TEPPEI TAKAHASHI
  • Patent number: 11151064
    Abstract: A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space; create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space; in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device; and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 19, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hideki Yoshida
  • Patent number: 11150835
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11144451
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11142661
    Abstract: The present invention relates to an ink-jet printing method using an apparatus including a printing means for ejecting a black ink to a printing substrate to print characters or images on the printing substrate, and a drying means disposed on a downstream side of a transportation direction of the printing substrate, in which the printing substrate is a label printing substrate; the black ink is a water-based composite black ink; the water-based composite black ink contains a composite black pigment containing carbon black, and a content of the carbon black in the composite black pigment is not more than 25% by mass; and the drying means is an infrared heater for heating the water-based composite black ink ejected onto the printing substrate to a temperature of not lower than 95° C. and not higher than 125° C.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 12, 2021
    Assignee: KAO CORPORATION
    Inventors: Tomoaki Il, Isao Tsuru, Norihiro Yoshida, Yoshiharu Niizeki, Jun Tairadate, Kimiya Yamada, Hideki Sakai
  • Publication number: 20210278974
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20210274102
    Abstract: An image processing apparatus that generates, from a captured image, a color temperature map that indicates color temperature information of light illuminating a captured scene for each area, is disclosed. The apparatus determines, for each area of the captured image, either an interactive light source that has a communication function, a non-interactive light source that does not have a communication function, or both of the interactive light source and the non-interactive light source is a light source that illuminates a corresponding area in the captured scene. The apparatus also generates the color temperature map using a result of determination made by the determining unit, color temperature information acquired from the interactive light source through communication, and color temperature information of the non-interactive light source that is estimated based on the captured image.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 2, 2021
    Inventors: Hideki Kadoi, Ryosuke Takahashi, Hiroaki Kuchiki, Akimitsu Yoshida, Kohei Furuya
  • Patent number: 11107915
    Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 31, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Chie Fujioka, Hiroshi Yoshida, Yoshihiro Matsushima, Hideki Mizuhara, Masao Hamasaki, Mitsuaki Sakamoto
  • Patent number: 11109494
    Abstract: A display device includes a control substrate provided in the display device, a first connecting part provided on the control substrate and connecting a controller to the control substrate, the controller configured to control the display device, and a second connecting part provided on the control substrate and connecting a user interface unit to the control substrate, the user interface unit connected to an external device.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 31, 2021
    Assignee: FANUC CORPORATION
    Inventors: Hideo Kobayashi, Kouhei Yoshida, Hiroyuki Suwa, Hideki Okamura
  • Patent number: 11093137
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11042487
    Abstract: According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11042305
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11042331
    Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida
  • Publication number: 20210042246
    Abstract: A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space; create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space; in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device; and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.
    Type: Application
    Filed: February 6, 2020
    Publication date: February 11, 2021
    Inventor: Hideki YOSHIDA
  • Publication number: 20210042033
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Patent number: 10903492
    Abstract: A method of producing a nickel-cobalt composite hydroxide includes: preparing a first solution containing nickel ions and cobalt ions; preparing a second solution containing tungsten ions and having a pH of 10 or more; preparing a third solution containing a complex ion-forming factor; preparing a liquid medium having a pH in a range of 10 to 13.5; supplying the first solution, the second solution, and the third solution separately and simultaneously to the liquid medium to obtain a reacted solution having a pH in a range of 10 to 13.5; and obtaining the nickel-cobalt composite hydroxide containing nickel, cobalt, and tungsten from the reacted solution.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 26, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
  • Patent number: 10866733
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Publication number: 20200363996
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20200364145
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10824217
    Abstract: According to one embodiment, a storage includes a nonvolatile memory and a controller configured to control the nonvolatile memory. The storage is supplied with first power from a power supply unit. The controller is configured to change power supplied from the power supply unit from the first power to second power based on a power control command transmitted from a host. The power control command includes a first parameter identifying the storage and a second parameter indicative of the second power.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Naoki Sawai, Hiroshi Murayama, Hiroshi Nishimura, Shinichi Kanno, Hideki Yoshida