Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240123229
    Abstract: Provided is an electrostimulation device that outputs an electrical signal, the electrical signal obtained by repeatedly outputting a fifth electrical signal comprising a first electrical signal whose amplitude in a first time becomes larger from a first amplitude, a second electrical signal whose amplitude in a second time is maintained to a second amplitude, a third electrical signal whose amplitude in a third time becomes smaller to a third amplitude, and a fourth electrical signal whose amplitude in a fourth time is maintained to a fourth amplitude; and the first electrical signal output in a sixth time, that is obtained by repeatedly outputting an eighth electrical signal comprising a sixth electrical signal having a first frequency, the sixth electrical signal that is off in a seventh time, wherein the first frequency is controlled via first frequency control of changing from a second frequency to a third frequency.
    Type: Application
    Filed: February 16, 2022
    Publication date: April 18, 2024
    Applicant: ITO CO., LTD.
    Inventors: Daigo YOSHIDA, Ryoichi TAKASU, Wataru ORITO, Osamu ITO, Hideki ARAI
  • Patent number: 11954043
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20240110282
    Abstract: A loadlock assembly is disclosed. Exemplary loadlock assembly includes a loadlock chamber provided with a plurality of sidewalls, a top portion, a bottom portion, and a plurality of openings through which a substrate is configured to be passed into the loadlock chamber; wherein the loadlock chamber is provided with a plurality of cooling gas intake ports; a substrate support disposed in the loadlock chamber and configured to support the substrate at or near an edge of the substrate; and a chiller unit provided with a plurality of cooling gas nozzles coupled to the cooling gas intake ports and configured to provide a cooling gas that passes through the plurality of cooling gas nozzles to the loadlock chamber.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventor: Hideki Yoshida
  • Patent number: 11947837
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11945729
    Abstract: A method for producing a nickel cobalt complex hydroxide includes first crystallization of supplying a solution containing Ni, Co and Mn, a complex ion forming agent and a basic solution separately and simultaneously to one reaction vessel to obtain nickel cobalt complex hydroxide particles, and a second crystallization of, after the first crystallization, further supplying a solution containing nickel, cobalt, and manganese, a solution of a complex ion forming agent, a basic solution, and a solution containing said element M separately and simultaneously to the reaction vessel to crystallize a complex hydroxide particles containing nickel, cobalt, manganese and said element M on the nickel cobalt complex hydroxide particles crystallizing a complex hydroxide particles comprising Ni, Co, Mn and the element M on the nickel cobalt complex hydroxide particles.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: April 2, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
  • Patent number: 11940463
    Abstract: The particle measurement device includes: an acquiring unit configured to acquire pad surface shape data indicating a surface shape of an electrode pad including a probe needle mark where a probe needle has contacted; a roughness calculating unit configured to calculate volume of a recessed portion recessed from a pad reference surface and volume of a protruding portion protruding from the pad reference surface based on the pad surface shape data; and a particle quantity calculating unit configured to calculate a particle quantity from a volume difference between the volume of the recessed portion and the volume of the protruding portion.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: March 26, 2024
    Assignee: TOKYO SEIMITSU CO., LTD.
    Inventors: Natsumi Hayashi, Hideki Morii, Tetsuo Yoshida, Toshiyuki Kimura
  • Publication number: 20240082413
    Abstract: As an antitumor drug which is excellent in terms of antitumor effect and safety, there is provided an antibody-drug conjugate in which an antitumor compound represented by the following formula is conjugated to an antibody via a linker having a structure represented by the following formula: -L1-L2-LP-NH—(CH2)n1-La-Lb-Lc- wherein the antibody is connected to the terminal of L1, and the antitumor compound is connected to the terminal of Lc with the nitrogen atom of the amino group at position 1 as a connecting position.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 14, 2024
    Applicant: DAIICHI SANKYO COMPANY, LIMITED
    Inventors: Takeshi MASUDA, Hiroyuki NAITO, Takashi NAKADA, Masao YOSHIDA, Shinji ASHIDA, Hideki MIYAZAKI, Yuji KASUYA, Koji MORITA, Yuki ABE, Yusuke OGITANI
  • Publication number: 20240061610
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Patent number: 11861218
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: January 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Publication number: 20230418739
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventors: Shinichi KANNO, Hideki YOSHIDA
  • Patent number: 11853178
    Abstract: According to one embodiment, a storage system includes a first storage including first nonvolatile memories storing data which is corrupted when data is read from the first nonvolatile memories, and a controller which controls the first storage. The controller reads data from a first nonvolatile memory at a first address, and determines that whether the read data is to be written back to the first storage or not.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20230376239
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Hideki YOSHIDA, Shinichi KANNO, Naoki ESAKA
  • Publication number: 20230372872
    Abstract: A support device includes an acquirer configured to acquire data indicating water quality information of water to be treated, a pressure to supply the water to be treated to a membrane filtration device, a transmembrane pressure at a filtration membrane, a permeation flux at the filtration membrane, a frequency and cleaning conditions for cleaning the filtration membrane with cleaning water, and an outputter configured to output an optimum value of a current permeation flux, and a frequency and cleaning conditions for cleaning the membrane filtration device with the cleaning water in the future based on the data indicating the water quality information of the water to be treated, the pressure to supply the water to be treated to the membrane filtration device, and the transmembrane pressure at the filtration membrane, that have been acquired by the acquirer, by using a learned determination model acquired by performing learning processing using the data acquired by the acquirer.
    Type: Application
    Filed: September 14, 2021
    Publication date: November 23, 2023
    Inventors: Yasuhiro MATSUI, Ryota KIMURA, Hideki YOSHIDA
  • Patent number: 11797436
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: October 24, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20230333978
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 19, 2023
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20230325112
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA
  • Publication number: 20230315294
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20230305701
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Shinichi KANNO, Hiroshi NISHIMURA, Hideki YOSHIDA, Hiroshi MURAYAMA
  • Publication number: 20230297290
    Abstract: A memory system includes a nonvolatile memory including memory dies, and a controller. The controller is configured to create a first virtual storage with a first part of the memory dies and a second virtual storage with a second part of the memory dies, and create a redundant logical domain spanning one or more memory dies corresponding to the first virtual storage and one or more memory dies corresponding to the second virtual storage. The memory controller is configured to, in response to a write command, store write data corresponding to the write command in a first region of the first virtual storage and in a second region of the second virtual storage, and return to the host a response including a first physical address of the first region and a second physical address of the second region.
    Type: Application
    Filed: August 29, 2022
    Publication date: September 21, 2023
    Inventors: Hideki YOSHIDA, Shinichi KANNO
  • Patent number: 11762580
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Hideki Yoshida, Shinichi Kanno, Naoki Esaka