Patents by Inventor Hideki Yoshida

Hideki Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220058117
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 24, 2022
    Inventors: Shinichi KANNO, Hideki YOSHIDA
  • Patent number: 11247330
    Abstract: Examples of a method for teaching a transportation position includes correcting the position of an alignment jig having a plurality of sloping surfaces relative to a susceptor pin projecting upwards from an upper surface of a susceptor by lowering a robot hand to bring one of the sloping surfaces into contact with the susceptor pin and causing the susceptor pin to slide on the sloping surfaces by virtue of an own weight of the aliment jig, detecting a position of the alignment jig before and after the positional correction of the alignment jig, and correcting a movement destination information by an amount corresponding to a difference between an initial position and a corrected position of the alignment jig.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: February 15, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Hideki Yoshida, Masaei Suwada
  • Patent number: 11237756
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Coiporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Patent number: 11220438
    Abstract: A method for producing a nickel cobalt complex hydroxide includes first crystallization of supplying a solution containing Ni, Co and Mn, a complex ion forming agent and a basic solution separately and simultaneously to one reaction vessel to obtain nickel cobalt complex hydroxide particles, and a second crystallization of, after the first crystallization, further supplying a solution containing nickel, cobalt, and manganese, a solution of a complex ion forming agent, a basic solution, and a solution containing said element M separately and simultaneously to the reaction vessel to crystallize a complex hydroxide particles containing nickel, cobalt, manganese and said element M on the nickel cobalt complex hydroxide particles crystallizing a complex hydroxide particles comprising Ni, Co, Mn and the element M on the nickel cobalt complex hydroxide particles.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 11, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
  • Patent number: 11215584
    Abstract: A material defect detection device that detects a material defect in a predetermined region of metallic equipment using a magnetic field distribution in the predetermined region measured by a magnetic sensor array including a plurality of magnetic sensors, the material defect detection device including: a processor that calculates a density distribution of magnetic dipoles in the predetermined region based on the magnetic field distribution and calculates a depth distribution of material defect in the predetermined region based on the density distribution of the magnetic dipoles.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 4, 2022
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Tetsuya Ishikawa, Hideki Yoshida
  • Publication number: 20210382648
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA
  • Publication number: 20210349632
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11150835
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11151064
    Abstract: A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space; create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space; in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device; and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 19, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hideki Yoshida
  • Patent number: 11144451
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Publication number: 20210278974
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11093137
    Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11042305
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11042331
    Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida
  • Patent number: 11042487
    Abstract: According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20210042033
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Publication number: 20210042246
    Abstract: A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space; create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space; in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device; and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.
    Type: Application
    Filed: February 6, 2020
    Publication date: February 11, 2021
    Inventor: Hideki YOSHIDA
  • Patent number: 10903492
    Abstract: A method of producing a nickel-cobalt composite hydroxide includes: preparing a first solution containing nickel ions and cobalt ions; preparing a second solution containing tungsten ions and having a pH of 10 or more; preparing a third solution containing a complex ion-forming factor; preparing a liquid medium having a pH in a range of 10 to 13.5; supplying the first solution, the second solution, and the third solution separately and simultaneously to the liquid medium to obtain a reacted solution having a pH in a range of 10 to 13.5; and obtaining the nickel-cobalt composite hydroxide containing nickel, cobalt, and tungsten from the reacted solution.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 26, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
  • Patent number: 10866733
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Publication number: 20200364145
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Inventors: Shinichi Kanno, Hideki Yoshida