Patents by Inventor Hideo Shimizu

Hideo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130302663
    Abstract: According to one embodiment provides an assembled battery which comprises electric cells each having a protruding electrode terminal, a bus bar which is connected to the electrode terminal, also electrically connected to the electrode terminal, and comprises an accommodating portion that has an opening and accommodates the electrode terminal along a protruding direction of the protruding portion from the opening, and a protruding portion which is formed on one of a peripheral surface of the electrode terminal along the protruding direction and an inner surface of the accommodating portion along the protruding direction, protrudes toward the other of the peripheral surface and the inner surface, extends in the protruding direction, and comes into contact with the other.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 14, 2013
    Applicant: Kabushiki Kaisha Toshba
    Inventors: Ryuuichi TERAMOTO, Noboru Koike, Yasuyuki Nagase, Hideo Shimizu, Takashi Murai, Takahiro Terada
  • Publication number: 20130252048
    Abstract: A battery includes a plurality of electrode members each having a positive electrode, a negative electrode and an insulating separator arranged between the positive electrode and the negative electrode, bus bars each electrically connected to electrode members, and a battery case that houses the electrode members.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryuuichi TERAMOTO, Hideo SHIMIZU, Noboru KOIKE, Tadashi SHUDO, Nobumitsu TADA, Satoshi WADA, Takahiro TERADA, Kuniaki YAMAMOTO
  • Publication number: 20130252075
    Abstract: According to one embodiment, battery assembly includes casing, accumulators, and conductive member. The conductive member has two first walls, two second walls, and third wall. One of the first walls is connected to one of a cathode and an anode of one of the accumulators, and extended along a front surface of the casing. Other one of the first walls is connected to one of the cathode and the anode of other one of the accumulators, and extended along the front surface. The second walls are connected to the first walls via two first curve portions, respectively, and extended in direction crossing the front surface. The third wall is connected to the second walls via two second curve portions, respectively, and extended over between the two second walls in direction along the front surface at a position apart from the front surface.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 26, 2013
    Inventors: Hideo Shimizu, Tadasu Ishii, Tatsumi Matsuo, Takahiro Terada, Takayuki Ogawa
  • Publication number: 20130244089
    Abstract: According to one embodiment, a secondary battery device includes a secondary battery cell, a case configured to accommodate the secondary battery cell, and foam coating layers sandwiched between an outer surface of the secondary battery cell and an inner surface of the case and configured to hold the secondary battery cell.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Inventors: Hideo Shimizu, Noboru Koike, Takashi Murai, Yasuyuki Nagase, Tadashi Shudo, Satoru Nawa, Takashi Kobayashi, Kazuyuki Kuroda
  • Publication number: 20130243191
    Abstract: According to an embodiment, an encryption key generating apparatus includes first to third calculators. The first calculator executes a first round operation to a first portion of first data. The second calculator executes the first round to a second portion of second data pieces. Each second data piece includes the first portion of the first data to which the first round operation has been completed and the second portion obtained by changing at least a part of the first data other than the first portion. At least a part of the second portion is different from that of each of the other second portions. The second calculator executes the first round operation to each second portion. The third calculator unit executes operations of the second and subsequent rounds to the second data pieces.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi Komano, Hideo Shimizu, Mitsuru Kanda, Yasuyuki Tanaka, Taichi Isogai
  • Patent number: 8538017
    Abstract: According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Endo, Hideo Shimizu, Yuichi Komano, Hanae Ikeda, Atsushi Shimbo
  • Publication number: 20130238931
    Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes an encrypting circuit for operating in a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, and a page buffer having a first region for storing the data being read out from the memory cell array, and a second region used when executing the operation.
    Type: Application
    Filed: September 5, 2012
    Publication date: September 12, 2013
    Inventors: Toshihiro SUZUKI, Noboru Shibata, Hideo Shimizu
  • Publication number: 20130202105
    Abstract: According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data.
    Type: Application
    Filed: August 7, 2012
    Publication date: August 8, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hideo SHIMIZU
  • Patent number: 8497400
    Abstract: Provide that a useful catalyst for homogeneous hydrogenation, particularly a catalyst for homogeneous asymmetric hydrogenation for hydrogenation, particularly asymmetric hydrogenation, which is obtainable with comparative ease and is excellent in economically and workability, and a process for producing a hydrogenated compound of an unsaturated compound, particularly an optically active compound using said catalyst with a high yield and optical purity.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 30, 2013
    Assignee: Takasago International Corporation
    Inventors: Hideo Shimizu, Daisuke Igarashi, Wataru Kuriyama, Yukinori Yusa
  • Patent number: 8481791
    Abstract: Provide that a useful catalyst for homogeneous hydrogenation, particularly a catalyst for homogeneous asymmetric hydrogenation for hydrogenation, particularly asymmetric hydrogenation, which is obtainable with comparative ease and is excellent in economically and workability, and a process for producing a hydrogenated compound of an unsaturated compound, particularly an optically active compound using said catalyst with a high yield and optical purity.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 9, 2013
    Assignee: Takasago International Corporation
    Inventors: Hideo Shimizu, Daisuke Igarashi, Wataru Kuriyama, Yukinori Yusa
  • Patent number: 8460975
    Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: June 11, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
  • Publication number: 20130116438
    Abstract: An object of the present invention is to provide a novel iridium complex, and to provide a novel catalyst having excellent performances in terms of enantioselectivity, catalytic activity, and the like. Provided is an iridium complex of the following general formula (1): IrHZ2(PP)(Q)m??(1) wherein Z represents a halogen atom, PP represents a bisphosphine, Q represents an amine, and m represents 1 or 2.
    Type: Application
    Filed: August 30, 2011
    Publication date: May 9, 2013
    Applicant: TAKASAGO INTERNATIONAL CORPORATION
    Inventors: Hideo Shimizu, Hideki Nara
  • Patent number: 8409743
    Abstract: A battery system includes a battery block, a cooling pipe, and a coolant feeding device. The battery block includes a plurality of rectangular batteries that have a width greater than a thickness and are securely arranged in array alignment by a battery holder. The cooling pipe cools the rectangular batteries of the battery block. The coolant feeding device feeds coolant to the cooling pipe. In the battery system, the cooling pipe is arranged on the surface of the battery block in a thermally-coupled state so that the rectangular batteries are cooled by the coolant, which is circulated through the cooling pipe.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 2, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Wataru Okada, Hideo Shimizu, Shinsuke Nakamura, Tomoyuki Omura
  • Patent number: 8409119
    Abstract: A walking assistance device including a pelvic frame (10) extending from a lower back to each lateral side of a user, and a belly belt (20) for securing the pelvic frame in position. A power generator (30) is attached to each lateral side of the pelvic frame. A power transmitting arm (40) can be attached to an output member (33) of the power generator simply by hooking an upper part of a base end (41) of the power transmitting arm onto an upper groove (38) of the output member, and pushing a latch member or a slider (46) provided in a lower part of the base end onto a lower groove (39) of the output member. The user wearing the pelvic frame (10) can easily attach the power transmitting arm (40) to the output end of the power generator (30) by easily using a single hand without requiring help.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: April 2, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Hideo Shimizu, Tatsuya Noda, Taiji Koyama
  • Patent number: 8401180
    Abstract: According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Komano, Hideo Shimizu, Koichi Fujisaki, Hideyuki Miyake, Atsushi Shimbo
  • Publication number: 20120316476
    Abstract: In a walking assistance device (10) that can transmit the power generated by a power generator (26, 28) to a femoral part of a user, a swing arm (60, 62) is attached to an output member of the power generator at a base end thereof, and is connected to a femoral support plate (68, 70) at a free end thereof via a pivot joint (64). The pivot joint includes a spherical projection (100) provided on the free end of the swing arm and a socket (112) provided on the femoral support plate, the socket defining a spherical recess (110) configured to receive the spherical projection to permit a tilting movement of the femoral support plate at least in two directions with respect to the free end of the swing arm. Thereby, the femoral support plate is enabled to accommodate the build and/or the movement of the femoral part of the user.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 13, 2012
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Hideo Shimizu, Hideaki Takahashi, Koji Okazaki
  • Publication number: 20120307997
    Abstract: According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N?1.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Inventors: Tsukasa Endo, Yuichi Komano, Koichi Fujisaki, Hideo Shimizu, Hanae Ikeda, Atsushi Shimbo
  • Patent number: 8289738
    Abstract: A switching power supply has a full-wave AC rectifier circuit; a chopper circuit including an inductor, a capacitor smoothing current from the inductor, and a switching device for on-off control of the current fed to the capacitor. The rectifier circuit further has an input voltage detector circuit detecting chopper circuit input voltage; an output voltage error detector circuit detecting an error between an output voltage from the chopper circuit and a set voltage; a current control signal generator circuit generating a current control signal in-phase with an input voltage detection signal having a waveform similar to the input voltage detection signal and an amplitude proportional to an output voltage error signal; a current detector circuit detecting inductor current flow; a frequency setting circuit; an oscillator circuit; and a switching control circuit switching the switching device based on oscillation circuit signal, the current control signal, and the current detection signal.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: October 16, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hideo Shimizu
  • Patent number: 8213200
    Abstract: In a switching power supply apparatus, multiplier 9 multiplies error voltage Verr generated in voltage error amplifier 8 and input voltage Vin to generate first threshold signal Vth1 in-phase with and similar to input voltage Vin and having an amplitude proportional to error voltage Verr. Second threshold signal generator circuit 14 generates second threshold signal Vth2 from first threshold signal Vth1. Switching device 7 is turned on and off so that the inductor current may change between first and second threshold signals Vth1 and Vth2. The switching frequency is detected and the proportional factor of first and second threshold signals Vth1 and Vth2 is changed to control the average switching frequency almost at a constant value for reducing the high frequency noises and the switching losses. The switching power supply apparatus facilitates reducing the noises and losses, improving the power factor thereof, and preventing the response performances thereof from being impaired.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: July 3, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hideo Shimizu
  • Publication number: 20120131078
    Abstract: According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideo Shimizu, Yuichi Komano, Koichi Fujisaki, Shinichi Kawamura