Abstract: According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.

Abstract: A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

Abstract: A semiconductor storage device includes a substrate, a first stacked body provided above the substrate and having a side portion configured in a staircase pattern, a plurality of columnar portions passing through the first stacked body, a second stacked body provided in an outer edge portion of the substrate, and a plurality of first slits. The first stacked body include a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked. The second stacked body includes the plurality of first insulating layers and the plurality of conductive layers that are alternately stacked. The plurality of first slits extends through the first and second stacked bodies in a direction intersecting a stacking direction of the first stacked body.

Abstract: In one embodiment, a semiconductor device includes a first substrate, a first transistor provided on an upper face of the first substrate, and a memory cell array provided above the first transistor. The device further includes a second substrate provided above the memory cell array, and a second transistor provided on an upper face of the second substrate.

Abstract: A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.

Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.

Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

Abstract: A semiconductor storage device includes: a first semiconductor layer through first conductive layers; a gate insulating film between the first conductive layers and the first semiconductor layer; a first structure facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layer and the first structure; a third semiconductor layer between the second semiconductor layer and the first conductive layers; a fourth semiconductor layer including a first portion along a bottom surface of the third semiconductor layer and a second portion along a top surface of the second semiconductor layer; and a first insulating layer, between the first and second portions, including a first region spaced from the first structure with a distance longer than a first distance that contains a nitride film, and a second region spaced from the first structure with a distance shorter than the first distance that does not contain nitrogen.

Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

Abstract: A semiconductor memory device includes: a stack having conductive layers and insulating layers, the conductive layers including a first select gate line connected to a gate of a first select transistor, a word line provided above the first select gate line and connected to a gate of a memory transistor, and a second select gate line provided above the word line and connected to a gate of a second select transistor; a core insulating layer having a top surface lower than a top surface of the second select gate line; a semiconductor layer having a first semiconductor part having channel formation regions of the transistors and a second semiconductor part on the top surface of the core insulating layer; and a memory layer between the semiconductor layer and the stack. The first semiconductor part has an impurity semiconductor region containing an impurity and overlapping with the second select gate line.

Abstract: A semiconductor device includes a substrate, a first external connection pad separated from the substrate in a first direction, which is a thickness direction thereof, a first coil separated from the substrate in the first direction and electrically connected to the connection pad, a first stacked body between the connection pad and the substrate and between the first coil and the substrate, the first stacked body including a first insulator, a first wiring therein, and a first pad electrically connected to the wiring, and a second stacked body between the first stacked body and the substrate, the second stacked body including a second insulator, a second wiring therein, a second pad electrically connected to the second wiring, and a second coil. The first insulator contacts the second insulator. The first pad contacts the second pad. A part of the first coil overlaps the second coil in the first direction.

Abstract: A semiconductor device includes a first substrate and a plurality of electrode layers above the first substrate and separated from each other in a first direction. The device includes a plurality of plugs provided on upper surfaces or lower surfaces of the plurality of electrode layers and a plurality of columnar portions in the plurality of electrode layers and extending in the first direction. A charge storage layer is between a semiconductor layer of the columnar portions and the electrode layers. A second substrate is provided above the plurality of electrode layers. A plurality of first transistors is provided on an upper surface of the first substrate and are electrically connected to the plurality of plugs. A plurality of second transistors is provided on a lower surface of the second substrate and are electrically connected to the plurality of columnar portions.

Abstract: A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.

Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

Abstract: According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.

Abstract: A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.

Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

Abstract: A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.