Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

Abstract: A nonvolatile semiconductor storage device is disclosed that includes a p-type semiconductor substrate, a gate insulating film formed above the semiconductor substrate, a memory-cell transistor and a peripheral circuit transistor formed above the gate insulating film. The memory-cell transistor includes a first gate electrode including a stack of a floating gate electrode comprising a p-type first polycrystalline silicon film, an interelectrode insulating film, and a control gate electrode comprising a p-type second polycrystalline silicon film. The peripheral circuit transistor includes a second gate electrode including a stack of a lower electrode comprising an n-type third polycrystalline silicon film; a first insulating film having an opening and being located above the lower electrode, an upper electrode comprising the same material as the second polycrystalline silicon film and contacting the third polycrystalline silicon film through the opening of the first insulating film.

Abstract: A nonvolatile semiconductor storage device including a memory cell region including a memory cell having a charge storing layer above a gate insulating film and a control electrode above the charge storing layer via an interelectrode insulating film; and a peripheral circuit region including a peripheral element having a first polysilicon and a first insulating film above the first polysilicon; wherein the charge storing layer includes a polysilicon doped with P-type impurity including a first upper region contacting the interelectrode insulating film and having a first doped layer doped with carbon or nitrogen, and at least a portion of a region below the first doped layer is neither doped with carbon nor nitrogen, and wherein the first polysilicon includes a second upper region contacting the first insulating film and having a second doped layer doped with carbon or nitrogen, the first and the second doped layers having equal thickness.

Abstract: A nonvolatile semiconductor storage device including memory-cell transistors located in a memory-cell region, each of the transistors including a gate insulating film formed on a semiconductor substrate and a memory-cell gate electrode including a first semiconductor film, an insulating film, and a conductive film; word lines each interconnecting the conductive film of the transistors aligned in a first direction and each including a hook-up portion located in a hook-up region located outside the memory-cell region; and an interlayer insulating film disposed on the upper surface of the memory-cell gate electrodes so as to form a gap between the memory-cell gate electrodes; wherein a second semiconductor film and a first insulating film are disposed in the hook-up region, wherein the interlayer insulating film covers an upper surface of the first insulating film and an upper surface of the plurality of word lines in the hook-up portion.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.

Abstract: A block dividing unit groups one-word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis.

Abstract: According to an embodiment, a nonvolatile memory device includes a plurality of memory cell strings disposed in parallel in a first direction, a bit line and a first contact plug. Each of the memory cell strings extends in a second direction orthogonal to the first direction and includes a plurality of memory cells disposed in parallel in the second direction. The bit line is shared by two adjacent memory cell strings of the memory cell strings, and the first contact plug is connected to the bit line and one of the two adjacent memory cell strings. The bit line includes a first transistor section controlling a current flowing in the one of the adjacent memory cell strings.

Abstract: A nonvolatile semiconductor memory device comprises multiple cell units that are arranged in the form of a matrix in the memory cell region, a bit line that is connected to the drain of one side of the selector gate transistor of each of the cell units and that is arranged in an extending direction of the multiple cell units, a source line that is connected to the source of the other side of the selector gate transistor of each of the cell units and that is arranged at right angle to the multiple cell units, and a bit line charge-discharge transistor that charges and discharges the bit line and that is arranged adjacent to the contact connected to the bit line on the region of drain side of at least one of the selector gate transistors of the multiple cell units.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors, a first select gate transistor and a second select gate transistor, word lines extending to the first direction, and a first insulating film formed on an upper surface of the memory cell array, a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor, wherein the first embedded wiring layer has an inclined pattern which extends in a direction not parallel to either of the first and the second directions.

Abstract: A nonvolatile semiconductor storage device including a semiconductor substrate; a first semiconductor region being formed in the semiconductor substrate and being delineated by a first element isolation trench filled with an isolation insulating film; a second semiconductor region being formed in the semiconductor substrate and being delineated by a second element isolation trench filled with the isolation insulating film; a memory cell transistor formed in the first semiconductor region, the memory cell transistor including a first gate insulating film, a memory gate electrode including a stack of, a first conductive film, a second gate insulating film, and a second conductive film formed above the first gate insulating film; a resistor formed in the second semiconductor region, the resistor including a stack of the first gate insulating film and the first conductive film; and a first and second contact plug contacting the first conductive film of the resistor.

Abstract: A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer.

Abstract: Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer.

Abstract: In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word line and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.

Abstract: According to an embodiment, a block dividing unit groups l word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

Abstract: A semiconductor storage device according to an embodiment includes a memory cell array provided on a semiconductor substrate and comprising a plurality of memory cells configured to store data therein, and a peripheral circuit part provided on the semiconductor substrate and configured to control the memory cell array. An element isolation part is provided between active areas where the memory cells and the peripheral circuit part are formed. A sidewall film is provided on a side surface of the active area in the peripheral circuit part.

Abstract: A semiconductor storage device according to an embodiment includes a memory cell comprising a charge accumulate layer above a semiconductor substrate and a control gate above the charge accumulate layer. The charge accumulate layer is capable of accumulating charges therein. The control gate is configured to control an amount of the charges accumulated in the charge accumulate layer. The control gate comprises a lower-layer control gate part of metal or metallic silicide which is processable by etching, and an upper-layer control gate part of a material different from that of the lower-layer control gate part.

Abstract: In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word line and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.