Abstract: Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer.

Abstract: A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages.