Abstract: A memory device comprises electrode layers stacked in a stacking direction. Semiconductor pillars penetrate the electrode layers in the stacking direction. First wirings are disposed above the plurality of electrode layers at a first level. Each first wiring is electrically connected to a semiconductor pillar. A second wiring is disposed above the plurality of electrode layers at the first level. The second wiring is insulated from semiconductor pillars. The second wiring and the first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction. A width of the second wiring the second direction is equal to a width of each first wiring. A spacing distance between the second wiring and a nearest first wiring is greater than a spacing interval between adjacent first wirings.

Abstract: According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.

Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and an interconnect portion. The interconnect portion is provided in the stacked body and extends in a stacking direction of a plurality of electrode layers and a first direction crossing the stacking direction. The interconnect portion includes a first portion located in a first region of the stacked body that the plurality of columnar portions is provided and a second portion located in a second region of the stacked body adjacent to the first region in the first direction, the first portion having a first width, the second portion having a second width larger than the first width.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and an interconnect portion. The interconnect portion is provided in the stacked body and extends in a stacking direction of a plurality of electrode layers and a first direction crossing the stacking direction. The interconnect portion includes a first portion located in a first region of the stacked body that the plurality of columnar portions is provided and a second portion located in a second region of the stacked body adjacent to the first region in the first direction, the first portion having a first width, the second portion having a second width larger than the first width.

Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.

Abstract: A nonvolatile semiconductor storage device a memory cell array including a plurality of memory cell units arranged in a matrix configuration, the memory cell units including a memory string including a series connection of a plurality of memory cells that stores data in accordance with a threshold voltage and is capable of electrical data writing and erasure, a first select gate transistor that connects a first end of the memory string to a bit line and a second select gate transistor that connects a second end of the memory string to a source line. The nonvolatile semiconductor storage device a discharge transistor that is connected between the bit line and the source line and causes discharge of the bit line to the source line.

Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.

Abstract: A nonvolatile semiconductor storage device a memory cell array including a plurality of memory cell units arranged in a matrix configuration, the memory cell units including a memory string including a series connection of a plurality of memory cells that stores data in accordance with a threshold voltage and is capable of electrical data writing and erasure, a first select gate transistor that connects a first end of the memory string to a bit line and a second select gate transistor that connects a second end of the memory string to a source line. The nonvolatile semiconductor storage device a discharge transistor that is connected between the bit line and the source line and causes discharge of the bit line to the source line.

Abstract: A nonvolatile semiconductor memory includes a memory cell array, the memory cell array including a memory string and a matrix of a plurality of memory cell units, the memory string containing a plurality of memory cells that are provided on the substrate, store data according to a threshold voltage, allow electrical writing and erasure of data, and are connected in series, the memory cell unit containing a first selecting gate transistor that connects a first end of the memory string to a bit line and a second selecting gate transistor that connects a second end of the memory string to a source line. After data is written in selected one of the memory cells, the voltage of the substrate is controlled for a specified period to be higher than a voltage of a word line connected to the selected memory cell.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a silicon substrate; and a plurality of memory cells that nonvolatilely accumulate a charge as data, disposed along at least a first direction, on the substrate. A diffusion layer is disposed continuously in a surface of the substrate of a region straddling the plurality of memory cells disposed along the first direction. The memory cell incudes an epitaxial silicon layer disposed on the diffusion layer.

Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.

Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.

Abstract: According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors.

Abstract: A semiconductor device including a memory cell region including a memory cell in which a floating electrode is disposed above a gate insulating film and a control electrode is stacked above the floating electrode via an interelectrode insulating film, wherein the floating electrode of the memory cell includes a first polysilicon layer containing nitrogen and a second polysilicon layer containing a P-type impurity, and wherein a height of an upper surface of an end of the first polysilicon layer is higher than a height of an upper surface of an element isolation insulating film disposed in the memory cell region.

Abstract: A semiconductor device includes, a semiconductor substrate, a plurality of memory cells being provided on the semiconductor substrate in a memory cell region. Each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, and a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.

Abstract: A nonvolatile semiconductor storage device including a memory cell region including a memory cell having a charge storing layer above a gate insulating film and a control electrode above the charge storing layer via an interelectrode insulating film; and a peripheral circuit region including a peripheral element having a first polysilicon and a first insulating film above the first polysilicon; wherein the charge storing layer includes a polysilicon doped with P-type impurity including a first upper region contacting the interelectrode insulating film and having a first doped layer doped with carbon or nitrogen, and at least a portion of a region below the first doped layer is neither doped with carbon nor nitrogen, and wherein the first polysilicon includes a second upper region contacting the first insulating film and having a second doped layer doped with carbon or nitrogen, the first and the second doped layers having equal thickness.

Abstract: According to one embodiment, nonvolatile semiconductor memory device includes: a semiconductor layer; element regions separated the semiconductor layer, the element regions; and a memory cell including a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode provided above the element regions, a peripheral region including a resistance element including a resistance element layer provided above the semiconductor layer via a first insulating film, a dummy layer provided on a part of the resistance element layer via a second insulating film, a third insulating film provided on the resistance element layer at a first distance from the dummy layer, a fourth insulating film provided on the semiconductor layer at a second distance from the resistance element layer, and a contact piercing the third insulating film, and connected to the resistance element layer, the first distance being shorter than the second distance.

Abstract: According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors.