Abstract: A storage system includes a controller and a nonvolatile memory drive, in which the controller transmits a write request that designates a volume identifier of a volume to be provided to a host, to the nonvolatile memory drive; the nonvolatile memory drive exclusively allocates a free block selected from a plurality of blocks to the volume identifier; write data of the write request is written to the free block; when the write data is update write data, an area that stores data to be updated is changed to an invalid data area; and after valid data of a block including the invalid data area is migrated to another block, all data of the block including the invalid data area is erased.

Abstract: A storage unit according to one aspect of the present invention comprises a storage controller and a plurality of storage devices. Each storage device has nonvolatile semiconductor memories serving as storage media. The controller of each storage device diagnoses the state of degradation of the nonvolatile semiconductor memories, and if one of the nonvolatile semiconductor memories is expected to be nearing end of life, then the controller copies the data stored in that degraded nonvolatile semiconductor memory to another nonvolatile semiconductor memory, and then performs shutdown processing for the degraded nonvolatile semiconductor memory, as well as storage capacity reduction processing.

Abstract: A disclosed method includes selecting one or more regions having a predetermined size or more in a logical address space of a first memory drive when the first memory drive is partially failed, transferring data of the one or more selected regions to a second memory drive, reading data from another memory drive, which forms a RAID group with the first memory drive, to restore lost data caused by the partial failure, and writing the restored lost data to the first memory drive.

Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.

Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.

Abstract: A semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.

Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.

Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.

Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.

Abstract: A storage device relating to one aspect of the present invention has a storage controller and multiple memory devices. The memory devices manage capacity equivalent to the size of a memory space provided to the storage controller among regions of a non-volatile storage medium as logical capacity and manage the remaining regions as reserve capacity. When a device controller determines that a portion of the memory regions in the non-volatile storage medium is in an unusable state, the device controller notifies the storage controller of the size of the memory regions in the unusable state. On the basis of a policy set by the memory device, the storage controller determines the reduction amount of the logical capacity and the reserve capacity and notifies the memory device of the determined reduction amount of the logical capacity.

Abstract: A storage unit according to one aspect of the present invention comprises a storage controller and a plurality of storage devices. Each storage device has nonvolatile semiconductor memories serving as storage media. The controller of each storage device diagnoses the state of degradation of the nonvolatile semiconductor memories, and if one of the nonvolatile semiconductor memories is expected to be nearing end of life, then the controller copies the data stored in that degraded nonvolatile semiconductor memory to another nonvolatile semiconductor memory, and then performs shutdown processing for the degraded nonvolatile semiconductor memory, as well as storage capacity reduction processing.

Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.

Abstract: A semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.

Abstract: A storage device comprises plural memory units and a storage controller that controls the memory units as a RAID group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g. flash memory) chip and a memory controller that compresses data and stores the compressed data into the nonvolatile semiconductor memory chips. The memory controller makes a logical memory area available to the storage controller. The storage controller divides the logical memory area into plural entries each of which is a logical memory area of a prescribed size, acquires from respective memory unit capacity information on the data capacity stored into the nonvolatile semiconductor memory, and exchanges data of entries between the semiconductor memory units on the basis of the capacity information.

Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.

Abstract: The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area.

Abstract: The present invention guarantees throughput for decompressing compressed data. A data compression apparatus includes: a division unit that divides plaintext data inputted to the division unit into a plurality of plaintext blocks each having a prescribed plaintext block length; a compression unit that creates a payload for each plaintext block of the plurality of plaintext blocks by compressing the plaintext block using a sliding dictionary-type compression algorithm, creates a header indicating the length of the payload, and creates a compression block that includes the header and the payload; and a concatenation unit that creates compressed data by concatenating a plurality of compression blocks created from the plurality of plaintext blocks.

Abstract: A storage apparatus is provided with a plurality of nonvolatile semiconductor storage media and a storage controller that is a controller that is coupled to the plurality of semiconductor storage media. The storage controller identifies a first semiconductor storage unit that is at least one semiconductor storage media and a second semiconductor storage unit that is at least one semiconductor storage media and that is provided with a remaining length of life shorter than that of the first semiconductor storage unit based on the remaining life length information that has been acquired. The storage controller moreover identifies a first logical storage region for the first semiconductor storage unit and a second logical storage region that is provided with a write load higher than that of the first logical storage region for the second semiconductor storage unit based on the statistics information that indicates the statistics that is related to a write for every logical storage region.