Patents by Inventor Hideyuki Koseki

Hideyuki Koseki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233880
    Abstract: The present invention guarantees throughput for decompressing compressed data. A data compression apparatus includes: a division unit that divides plaintext data inputted to the division unit into a plurality of plaintext blocks each having a prescribed plaintext block length; a compression unit that creates a payload for each plaintext block of the plurality of plaintext blocks by compressing the plaintext block using a sliding dictionary-type compression algorithm, creates a header indicating the length of the payload, and creates a compression block that includes the header and the payload; and a concatenation unit that creates compressed data by concatenating a plurality of compression blocks created from the plurality of plaintext blocks.
    Type: Application
    Filed: August 9, 2013
    Publication date: August 11, 2016
    Applicant: HITACHI, LTD.
    Inventors: Nagamasa MIZUSHIMA, Hideyuki KOSEKI, Atsushi KAWAMURA
  • Patent number: 9405478
    Abstract: A storage apparatus is provided with a plurality of nonvolatile semiconductor storage media and a storage controller that is a controller that is coupled to the plurality of semiconductor storage media. The storage controller identifies a first semiconductor storage unit that is at least one semiconductor storage media and a second semiconductor storage unit that is at least one semiconductor storage media and that is provided with a remaining length of life shorter than that of the first semiconductor storage unit based on the remaining life length information that has been acquired. The storage controller moreover identifies a first logical storage region for the first semiconductor storage unit and a second logical storage region that is provided with a write load higher than that of the first logical storage region for the second semiconductor storage unit based on the statistics information that indicates the statistics that is related to a write for every logical storage region.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: August 2, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Koseki, Junji Ogawa
  • Patent number: 9335929
    Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 10, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
  • Publication number: 20160011938
    Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.
    Type: Application
    Filed: August 30, 2013
    Publication date: January 14, 2016
    Applicant: Hitachi, Ltd.
    Inventors: Hideyuki KOSEKI, Takashi TSUNEHIRO, Junji OGAWA, Nagamasa MIZUSHIMA, Atsushi KAWAMURA
  • Publication number: 20150378613
    Abstract: A storage device comprises plural memory units and a storage controller that controls the memory units as a RAID group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g. flash memory) chip and a memory controller that compresses data and stores the compressed data into the nonvolatile semiconductor memory chips. The memory controller makes a logical memory area available to the storage controller. The storage controller divides the logical memory area into plural entries each of which is a logical memory area of a prescribed size, acquires from respective memory unit capacity information on the data capacity stored into the nonvolatile semiconductor memory, and exchanges data of entries between the semiconductor memory units on the basis of the capacity information.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 31, 2015
    Inventor: Hideyuki KOSEKI
  • Patent number: 9128847
    Abstract: A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: September 8, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Ito, Junji Ogawa, Hideyuki Koseki
  • Publication number: 20150106555
    Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Applicant: Hitachi, Ltd.
    Inventors: ATSUSHI ISHIKAWA, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
  • Publication number: 20150100721
    Abstract: The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventor: Hideyuki KOSEKI
  • Patent number: 8949511
    Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
  • Patent number: 8943266
    Abstract: The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Patent number: 8924659
    Abstract: The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 30, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Publication number: 20140281168
    Abstract: The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventor: Hideyuki Koseki
  • Patent number: 8799745
    Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Patent number: 8713251
    Abstract: A disk array device that can detect the successful completion of data overwrite/update at high speed only by checking a UDT is provided. When a DIF is used as a verification code appended to data, check information that detects the successful completion of overwrite is defined in the UDT, in addition to address information that detects positional errors. Upon request of overwrite/update of data stored in a cache, a check bit of the data in the cache is changed to a value different from a check bit to be appended to new data by a host adapter. Then, data transfer is initiated. Upon completion of the data overwrite, the check bit is changed back to the original value, whereby it is possible to detect the successful completion of overwrite/update (FIG. 8).
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: April 29, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Koseki, Yusuke Nonaka
  • Publication number: 20140115235
    Abstract: A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Inventors: Yuji Ito, Junji Ogawa, Hideyuki Koseki
  • Publication number: 20140026013
    Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.
    Type: Application
    Filed: April 12, 2011
    Publication date: January 23, 2014
    Applicant: HITACHI, LTD.
    Inventor: Hideyuki Koseki
  • Publication number: 20130346829
    Abstract: When writing data to a first-type FM part, an FM controller of a flash memory device (A1) generates a redundant code, and (A2) writes the data and the redundant code. when reading the written data, the flash memory controller (B1) reads the data and the redundant code, (B2) corrects any bit errors based on the redundant code, (B3) generates error correction information including positions of the bit errors occurring and values before the bit errors occurred, and (B4) writes the error correction information to a second-type FM part.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Inventor: Hideyuki Koseki
  • Patent number: 8601347
    Abstract: When writing data to a first-type FM part, an FM controller of a flash memory device (A1) generates a redundant code, and (A2) writes the data and the redundant code, when reading the written data, the flash memory controller (B1) reads the data and the redundant code, (B2) corrects any bit errors based on the redundant code, (B3) generates error correction information including positions of the bit errors occurring and values before the bit errors occurred, and (B4) writes the error correction information to a second-type FM part. Subsequently, when reading the data, the flash memory controller (C1) reads the data and the redundant code, (C2) reads the error correction information, (C3) corrects the data and the redundant code based on the error correction information, (C4) corrects any bit errors based on the corrected redundant code.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Publication number: 20130205070
    Abstract: A storage apparatus is provided with a plurality of nonvolatile semiconductor storage media and a storage controller that is a controller that is coupled to the plurality of semiconductor storage media. The storage controller identifies a first semiconductor storage unit that is at least one semiconductor storage media and a second semiconductor storage unit that is at least one semiconductor storage media and that is provided with a remaining length of life shorter than that of the first semiconductor storage unit based on the remaining life length information that has been acquired. The storage controller moreover identifies a first logical storage region for the first semiconductor storage unit and a second logical storage region that is provided with a write load higher than that of the first logical storage region for the second semiconductor storage unit based on the statistics information that indicates the statistics that is related to a write for every logical storage region.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Inventors: Hideyuki Koseki, Junji Ogawa
  • Patent number: 8489813
    Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki