Patents by Inventor Hideyuki Koseki
Hideyuki Koseki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8458400Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: GrantFiled: July 5, 2012Date of Patent: June 4, 2013Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Publication number: 20130086305Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Inventors: Atsushi Ishikawa, Koji Sonoda, Go Uehara, Junji Ogawa, Hideyuki Koseki
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Patent number: 8392670Abstract: The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible.Type: GrantFiled: April 12, 2010Date of Patent: March 5, 2013Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Patent number: 8387063Abstract: This storage apparatus having a plurality of physical devices for balancing and retaining data sent from a host computer and parity of the data for each prescribed unit includes a load ratio calculation unit for calculating a load ratio of the plurality of physical devices, a load ratio determination unit for determining whether the load ratio of the physical devices calculated with the load ratio calculation unit exceeds a prescribed threshold value, a command ratio determination unit for determining whether a command ratio of either a write command or a read command issued from the host computer exceeds a prescribed threshold value when the load ratio determination unit determines that the load ratio of the physical device exceeds a prescribed threshold value, and a change unit for changing the data and the parity among the plurality of physical devices when the command ratio determination unit determines that the command ratio exceeds a prescribed threshold value.Type: GrantFiled: November 14, 2006Date of Patent: February 26, 2013Assignee: Hitachi, Ltd.Inventors: Hideyuki Koseki, Junji Ogawa
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Publication number: 20120278556Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: ApplicationFiled: July 5, 2012Publication date: November 1, 2012Inventor: Hideyuki KOSEKI
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Publication number: 20120271992Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.Type: ApplicationFiled: July 3, 2012Publication date: October 25, 2012Inventor: Hideyuki KOSEKI
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Patent number: 8296516Abstract: A first controller has a first CM area having a plurality of first sub-areas, and a second controller has a second CM area having a plurality of second sub-areas. The first controller stores first data in any of the first sub-areas, and in addition, stores a mirror of the first data (first mirror data) in any of the second sub-areas. The first controller manages a pair (an association relationship) of the storage-destination first sub-area of the first data and the storage-destination second sub-area of the first mirror data. Similarly, the second controller stores second data in any of the second sub-areas, and in addition, stores a mirror of the second data (second mirror data) in any of the first sub-areas. The second controller manages a pair (an association relationship) of the storage-destination second sub-area of the second data and the storage-destination first sub-area of the second mirror data.Type: GrantFiled: October 20, 2009Date of Patent: October 23, 2012Assignee: Hitachi, Ltd.Inventors: Atsushi Kawamura, Yusuke Nonaka, Hideyuki Koseki
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Patent number: 8239626Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.Type: GrantFiled: April 8, 2011Date of Patent: August 7, 2012Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Patent number: 8239630Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: GrantFiled: June 2, 2011Date of Patent: August 7, 2012Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Publication number: 20110289280Abstract: A disk array device that can detect the successful completion of data overwrite/update at high speed only by checking a UDT is provided. When a DIF is used as a verification code appended to data, check information that detects the successful completion of overwrite is defined in the UDT, in addition to address information that detects positional errors. Upon request of overwrite/update of data stored in a cache, a check bit of the data in the cache is changed to a value different from a check bit to be appended to new data by a host adapter. Then, data transfer is initiated. Upon completion of the data overwrite, the check bit is changed back to the original value, whereby it is possible to detect the successful completion of overwrite/update (FIG. 8).Type: ApplicationFiled: May 27, 2009Publication date: November 24, 2011Inventors: Hideyuki Koseki, Yusuke Nonaka
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Publication number: 20110283046Abstract: The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible (see FIG. 16).Type: ApplicationFiled: April 12, 2010Publication date: November 17, 2011Applicant: HITACHI, LTD.Inventor: Hideyuki Koseki
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Publication number: 20110231369Abstract: A first controller has a first CM area having a plurality of first sub-areas, and a second controller has a second CM area having a plurality of second sub-areas. The first controller stores first data in any of the first sub-areas, and in addition, stores a mirror of the first data (first mirror data) in any of the second sub-areas. The first controller manages a pair (an association relationship) of the storage-destination first sub-area of the first data and the storage-destination second sub-area of the first mirror data. Similarly, the second controller stores second data in any of the second sub-areas, and in addition, stores a mirror of the second data (second mirror data) in any of the first sub-areas. The second controller manages a pair (an association relationship) of the storage-destination second sub-area of the second data and the storage-destination first sub-area of the second mirror data.Type: ApplicationFiled: October 20, 2009Publication date: September 22, 2011Applicant: HITACHI, LTD.Inventors: Atsushi Kawamura, Yusuke Nonaka, Hideyuki Koseki
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Publication number: 20110231611Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Inventor: Hideyuki KOSEKI
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Publication number: 20110185124Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.Type: ApplicationFiled: April 8, 2011Publication date: July 28, 2011Inventor: Hideyuki KOSEKI
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Patent number: 7979639Abstract: Optimizing cache-resident area where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. An LU is a logical space resident in cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size. When the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: GrantFiled: December 10, 2008Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Patent number: 7945732Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device withal lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.Type: GrantFiled: January 4, 2008Date of Patent: May 17, 2011Assignee: Hitachi, Ltd.Inventor: Hideyuki Koseki
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Publication number: 20100100680Abstract: The object of the present invention is to provide a storage apparatus capable of optimizing the cache-resident area in a case where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. In the storage apparatus, in a case where an LU that is a logical space resident in the cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size, when the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory.Type: ApplicationFiled: December 10, 2008Publication date: April 22, 2010Inventor: Hideyuki Koseki
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Publication number: 20080313398Abstract: One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device withal lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.Type: ApplicationFiled: January 4, 2008Publication date: December 18, 2008Inventor: Hideyuki KOSEKI
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Patent number: 7380090Abstract: A storage device according to the present invention has a first volume for storing discontinuous data transmitted from a host computer and a second volume for storing continuous data produced by address-converting discontinuous data, and includes: a data storing unit for converting the discontinuous data transmitted from the host computer into the continuous data and storing the continuous data in one of a plurality of third volumes formed by dividing up the second volume; a data management unit for managing transfer target data that has to be transferred from the third to the first volume, from among the discontinuous data stored in the third volume by the data storing unit; and a volume clearance unit for clearing the third volume having the smallest amount of transfer target data managed by the data management unit by transferring the transfer target data in the relevant third volume to the first volume.Type: GrantFiled: April 14, 2006Date of Patent: May 27, 2008Assignee: Hitachi, Ltd.Inventors: Hideyuki Koseki, Junji Ogawa, Yutaka Nakagawa
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Publication number: 20080092143Abstract: This storage apparatus having a plurality of physical devices for balancing and retaining data sent from a host computer and parity of the data for each prescribed unit includes a load ratio calculation unit for calculating a load ratio of the plurality of physical devices, a load ratio determination unit for determining whether the load ratio of the physical devices calculated with the load ratio calculation unit exceeds a prescribed threshold value, a command ratio determination unit for determining whether a command ratio of either a write command or a read command issued from the host computer exceeds a prescribed threshold value when the load ratio determination unit determines that the load ratio of the physical device exceeds a prescribed threshold value, and a change unit for changing the data and the parity among the plurality of physical devices when the command ratio determination unit determines that the command ratio exceeds a prescribed threshold value.Type: ApplicationFiled: November 14, 2006Publication date: April 17, 2008Inventors: Hideyuki Koseki, Junji Ogawa