Abstract: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND cell unit by turning on the first and second select gate transistors, applying a predetermined voltage level on the source line, detecting a voltage level of the bit line at once under a state where a voltage level applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the second select gate transistor is arranged higher than that applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the first select gate transistor, and verifying data erase based on the detected voltage.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region being adjacent to the first region; a floating gate electrode layer formed above the semiconductor substrate in the first region, the floating gate electrode layer including a first width; a dummy gate electrode layer formed above the semiconductor substrate in the second region, the dummy gate electrode layer including a second width being greater than the first width of the floating gate electrode layer; a first gate insulating film formed on the floating gate electrode layer, the first gate insulating film including a first thickness; a second gate insulating film formed on the dummy gate electrode layer, the second gate insulating film including a second thickness being greater than the first thickness of the first gate insulating film; and a control gate electrode layer formed on the first and the second gate insulating films.

Abstract: A semiconductor device including a semiconductor substrate, a memory cell transistor formed in a memory cell region of the semiconductor substrate; a transistor formed in a peripheral circuit region of the semiconductor substrate and having an LDD (Lightly Doped Drain) structure; and the memory cell transistor has a same film thickness for an insulating film formed in a source/drain region and an insulating film formed or a gate electrode sidewall; and the transistor having the LDD structure is provided with a spacer insulating film on the gate electrode sidewall.

Abstract: A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in aeries together is disclosed. A select gate translator is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate translator is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device is provided having a plurality of electrically rewritable nonvolatile memory cells connected in series together. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with a different bias voltage as that for the other memory cells.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.

Abstract: A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type isolation region is formed between columns in the array of the NAND columns. The trench-type isolation region is formed in self-alignment with end portions of the channel region and a floating gate of the memory cell transistor, formed in self-alignment with the end portion of a channel region of the select transistor, and has a recess formed in at least the upper surface between the floating gates of the memory cell transistors.

Abstract: A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing an oxide film, forming a nitride film and an interlayer insulation film after the resist pattern has been removed, forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be formed in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.

Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Abstract: A nonvolatile semiconductor memory device includes erasable and programmable memory cell transistors, a selection transistor, a peripheral transistor, first post-oxidation films each provided on a gate electrode of all of the plurality of erasable and programmable memory cell transistors, a second post-oxidation film provided on a gate electrode of the selection transistor, a third post-oxidation film provided on a gate electrode of the peripheral transistor, and an insulating film covering the memory cell transistors, the selection transistor, and the peripheral transistor. The insulating film is harder for an oxidizing agent to pass through than a silicon oxide film. The insulating film has an oxidized region. The insulating film includes a silicon nitride film. The oxidized region is provided in a surface of the silicon nitride film.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: In a nonvolatile semiconductor storage device which is electrically writable and erasable, a silicon substrate, a plurality of element isolation portions which project from the silicon substrate and are disposed at a predetermined interval, floating electrodes disposed between the isolation portions, and a control electrode laminated on the isolation portions and the floating electrodes are provided, and an interval between the adjacent floating electrodes is formed greater at the side away from the silicon substrate than at the silicon substrate side.