Patents by Inventor Hiroaki Hazama

Hiroaki Hazama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5837405
    Abstract: In a reticle, a semi-transparent film pattern in place of a light blocking film pattern is used as a mask pattern having a size within a certain range, whereby an exposure system can be improved in resolution limit and faithful pattern transfer can be realized with a constant light quantity. A reticle may be of a stacked layer structure which comprises a shift film for providing a different optical path to exposure light, a mask substrate formed on the top or bottom of the shift film, and a transmissivity ratio adjustment layer having a predetermined transmissivity ratio to the exposure light. The material of a phase shifter may be adjusted in amplitude transmissivity ratio so that a shifter width for effectively improving a contrast can be made large and an accuracy necessary for a shifter width can be loosened.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: November 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Tomofuji, Makoto Nakase, Takashi Sato, Hiroaki Hazama, Haruki Komano, Shinichi Ito
  • Patent number: 5815436
    Abstract: A nonvolatile semiconductor memory device includes a memory cell including a charge storage section for storing n-value data (n.gtoreq.3). In this device, the charge storage section has discrete first to n-th charge amount regions for storing the n-value data. If the first to n-th charge amount regions are defined as n-th, (n-1)-th, . . . , (i+1)-th, i-th charge amount regions descending order of an amount of positive or negative charge stored in the charge storage section, a charge amount difference .DELTA.Mj between a j-th charge amount region and a (j-1)-th charge amount region is set to .DELTA.Mn >.DELTA.Mn-1> . . . >.DELTA.Mi+2>.DELTA.Mi+1.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: September 29, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoharu Tanaka, Hiroaki Hazama
  • Patent number: 5728494
    Abstract: This invention provides an exposure mask including a translucent film formed on a light-transmitting substrate and having a mask pattern, and a stabilized region formed in the boundary between the light-transmitting substrate and the translucent film or on at least the surface of the translucent film to prevent variations in physical properties of the translucent film.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: March 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Iwao Higashikawa, Masamitsu Itoh, Takashi Kamo, Hiroaki Hazama, Takayuki Iwamatsu
  • Patent number: 5660956
    Abstract: In a reticle, a semi-transparent film pattern in place of a light blocking film pattern is used as a mask pattern having a size within a certain range, whereby an exposure system can be improved in resolution limit and faithful pattern transfer can be realized with a constant light quantity. A reticle may be of a stacked layer structure which comprises a shift film for providing a different optical path to exposure light, a mask substrate formed on the top or bottom of the shift film, and a transmissivity ratio adjustment layer having a predetermined transmissivity ratio to the exposure light. The material of a phase shifter may be adjusted in amplitude transmissivity ratio so that a shifter width for effectively improving a contrast can be made large and an accuracy necessary for a shifter width can be loosened.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Tomofuji, Makoto Nakase, Takashi Sato, Hiroaki Hazama, Haruki Komano, Shinichi Ito
  • Patent number: 5629115
    Abstract: This invention provides an exposure mask including a translucent film formed on a light-transmitting substrate and having a mask pattern, and a stabilized region formed in the boundary between the light-transmitting substrate and the translucent film or on at least the surface of the translucent film to prevent variations in physical properties of the translucent film.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawano, Shinichi Ito, Iwao Higashikawa, Masamitsu Itoh, Takashi Kamo, Hiroaki Hazama, Takayuki Iwamatsu
  • Patent number: 5595844
    Abstract: In a reticle, a semi-transparent film pattern in place of a light blocking film pattern is used as a mask pattern having a size within a certain range, whereby an exposure system can be improved in resolution limit and faithful pattern transfer can be realized with a constant light quantity. A reticle may be of a stacked layer structure which comprises a shift film for providing a different optical path to exposure light, a mask substrate formed on the top or bottom of the shift film, and a transmissivity ratio adjustment layer having a predetermined transmissivity ratio to the exposure light. The material of a phase shifter may be adjusted in amplitude transmissivity ratio so that a shifter width for effectively improving a contrast can be made large and an accuracy necessary for a shifter width can be loosened.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: January 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Tomofuji, Makoto Nakase, Takashi Sato, Hiroaki Hazama, Haruki Komano, Shinichi Ito
  • Patent number: 5589305
    Abstract: In a reticle, a semi-transparent film pattern in place of a light blocking film pattern is used as a mask pattern having a size within a certain range, whereby an exposure system can be improved in resolution limit and faithful pattern transfer can be realized with a constant light quantity. A reticle may be of a stacked layer structure which comprises a shift film for providing a different optical path to exposure light, a mask substrate formed on the top or bottom of the shift film, and a transmissivity ratio adjustment layer having a predetermined transmissivity ratio to the exposure light. The material of a phase shifter may be adjusted in amplitude transmissivity ratio so that a shifter width for effectively improving a contrast can be made large and an accuracy necessary for a shifter width can be loosened.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: December 31, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Tomofuji, Makoto Nakase, Takashi Sato, Hiroaki Hazama, Haruki Komano, Shinichi Ito
  • Patent number: 5514904
    Abstract: A semiconductor device includes a monocrystalline silicon substrate, an insulating film consisting of a monocrystalline silicon oxide formed on the surface of the monocrystalline silicon substrate, and a conductive film formed on the insulating film. The monocrystalline silicon substrate has a (100) plane orientation, the insulating film essentially consists of .beta.-cristobalite having a unit structure in a P4.sub.1 2.sub.1 2 structural expression in such a manner that every other silicon atoms of four silicon atoms aligned about a C-axis are arranged on two adjacent silicon atoms aligned in a 110! direction on an Si (100) plane, and that a plane including the C-axis of the .beta.-cristobalite and the 110! direction is set perpendicular to the (100) plane.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Onga, Takako Okada, Kouichirou Inoue, Yoshiaki Matsushita, Kikuo Yamabe, Hiroaki Hazama, Haruo Okano
  • Patent number: 5162880
    Abstract: A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and connected to a bit line, an insulation film in which carrier traps are formed, and a gate electrode that is opposite the high-concentration impurity region across the insulation film and connected to a word line. Carriers are captured by, and released from, the carrier traps formed in the insulation film, in response to bias voltages applied to the word and bit lines. Information stored in the memory cell depends on whether or not the carrier traps are holding carriers. The information is read out of the memory cell as the difference of a tunneling current flowing between the semiconductor substrate and the high-concentration impurity region.
    Type: Grant
    Filed: September 27, 1990
    Date of Patent: November 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Hazama, Kazumi Nishinohara