Patents by Inventor Hiroaki Nakanishi

Hiroaki Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6104057
    Abstract: An electrically alterable non-volatile memory device is disclosed. In the device architecture of the memory device, control gates are formed, divided corresponding to the blocks and interconnected independently within each block, to further be connected to a metal gate line through block select MOS transistors which are formed on a semiconductor substrate between the blocks. All gate electrodes of the block select MOS transistors which are connected to the control gates interconnected as above within each block are further connected each other. These block select transistors can be controlled by applying erase block signals such as, EBS0, EBS1 and so on, to respective transistors. In addition, the control gates are further connected to a decoder such that some of these control gates may be selected through metal control gate lines.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroaki Nakanishi, Kunio Matsudaira, Masahiro Matsuo, Hirohisa Abe, Yoichi Sakai
  • Patent number: 6075267
    Abstract: A non-volatile semiconductor memory device includes a substrate and a continuously formed drain diffusion layer and a continuously formed source diffusion layer which are alternately arranged within the substrate. Floating gates are disposed via a tunnel insulating film on the substrate so that they are adjacent to the drain diffusion layer. The floating gates are opposed to each other with the drain diffusion layer therebetween, and spaced away from the source diffusion layer. A control gate extends in a direction orthogonal with a direction in which the source and drain diffusion layers extend, the control gate being formed on the floating gates and the substrate via an insulating film. A select channel is provided between the floating gate closest to the source diffusion layer and the source diffusion layer. A thick insulating film is provided between the drain diffusion layer and the control gate between the floating gates which are opposed to each other with the drain diffusion layer therebetween.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: June 13, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Satoru Taji, Hiroaki Nakanishi
  • Patent number: 6042708
    Abstract: In order to irradiate a constant range of a separation passage of a microchip, light from a light source linearly extending along the separation passage is transmitted through a cylindrical lens and a bandpass filter and introduced into the separation passage. The light transmitted through the separation passage of the microchip is introduced into a photocell array through a cylindrical lens and detected. Measurement is repetitively performed and accumulated to determine migration patterns.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: March 28, 2000
    Assignee: Shimadzu Corporation
    Inventors: Hiroaki Nakanishi, Akihiro Arai, Yosuke Iwata
  • Patent number: 6030883
    Abstract: At a room temperature, cleaned glass substrates 8a, 8b are suitably positioned and placed one upon another. A hydrofluoric acid solution or alkaline solution 10 is dropped into the bonding interface between the glass substrates 8a, 8b. The hydrofluoric acid solution or alkaline solution thus dropped spreads along the bonding interface. At a room temperature, a load is then applied to the upper glass substrate 8a and allowed to stand for a suitable period of time, thus bonding the glass substrates to each other.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: February 29, 2000
    Assignee: Shimadzu Corporation
    Inventors: Takahiro Nishimoto, Hiroaki Nakanishi
  • Patent number: 5966325
    Abstract: A memory cell of a memory device is constructed such that a source diffusion layer is divided into blocks each containing 16 word lines, and such that a drain diffusion layer is not divided. Each segment of the source diffusion layer is connected to a metal bit line via a block selection MOS transistor. The metal bit line is formed on an insulating film provided on the source diffusion layer so as to be parallel with the source diffusion layer. The block selection MOS transistor is connected to the metal bit line via a contact hole. A gate electrode of the block selection MOS transistor is formed of a polysilicon film for providing a selection gate used to form a word line of the memory cell. A source diffusion layer and a drain diffusion layer of the block selection MOS transistor are formed of the same material as the source diffusion layer of the memory cell and the drain diffusion layer of the memory cell.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: October 12, 1999
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroaki Nakanishi, Satoru Taji
  • Patent number: 5959728
    Abstract: A detector cell in which a pair of glass substrates are used, in which a groove is formed in the surface of at least one of the glass substrates, which has a sample passage formed by the bonding method above-mentioned, a sample inlet port and a sample outlet port, and in which at least a portion of the passage is used as a measuring chamber. There is also formed an optical measuring apparatus having the detector cell above-mentioned and arranged to measure light transmitted through a sample flowing in the passage. According to the arrangement above, it is possible to readily mutually bond, at room temperature, substrates made of a material of glass, quartz or the like of which at least bonding surfaces contain silicon dioxide as the primary component. Further, the optical measuring apparatus having a detector cell produced using this bonding method can achieve a highly precise analysis.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: September 28, 1999
    Assignee: Shimadzu Corporation
    Inventors: Takahiro Nishimoto, Hiroaki Nakanishi
  • Patent number: 5859977
    Abstract: A computer system is so configured as to be divided into a control system which should have high reliability and high responsiveness and an information system which does not access the control system. They are connected via a transmission path (transmission path of control system and transmission path of information system). Centralized management of development and maintenance is performed from a software maintenance system. In development and maintenance of software, management according to the feature of each software such as processing contents of each software, demanded reliability, and version up frequency is performed from a maintenance system for exclusive use by using a transmission path of information system. Thereby, development and maintenance having high reliability and expandability is realized.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: January 12, 1999
    Assignees: Hitachi, Ltd., Hitachi Process Engineering, Inc.
    Inventors: Shuji Nishiyama, Hiroaki Nakanishi, Hideki Sato, Hiroshi Kobayashi, Shigeru Endo, Toshimasa Saika, Teruyasu Nakahashi, Hiroyuki Hori, Tomohito Ebina, Keiichi Sannomiya, Shimako Tanno
  • Patent number: 5818823
    Abstract: A slot assign system has a central station and a plurality of peripheral stations, and the communication between them is made through an artificial satellite. The central station stores pre-assign slot information of each of the peripheral stations, and multiplexes slot assign information to be changed at a next frame over the pre-assign slot information. The peripheral station, on receipt of the slot assign information, transmits the next frame using a slot assigned to itself. The central station sends a vacant slot with no pre-assignment as a non-assign information signal, and the peripheral station recognizing the vacant slot transmits, using the slot assigned to itself, a reservation request for using the vacant slot. The central station transmits a frame next to the frame to which the slot has been assigned.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventor: Hiroaki Nakanishi
  • Patent number: 5815258
    Abstract: A liquid sample cell used in an optical measurement apparatus in which a liquid sample flows through a flow path of the sample cell while a measurement light travels through the liquid sample in the flow path. The liquid sample cell is composed of: a first glass plate and a second glass plate fixed to each other; a groove for constituting the flow path formed in the first glass plate by a photolithographic method; reflection layers formed on the internal surface of the groove and on the internal surface of the other glass plate; and an entrance window and an exit window formed in the reflection layers to let the measurement light into the flow path and to let the measurement light out from the flow path. The measurement light is reflected by the reflection layers many times in the flow path.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: September 29, 1998
    Assignee: Shimadzu Corporation
    Inventor: Hiroaki Nakanishi
  • Patent number: 5740424
    Abstract: There is disclosed an information processing system and method capable of coping with a wider range of subjects and intricate changes. In client server structure, time-varying database altering information received from external systems is pooled in servers and distributed to a number of distributed terminals or clients, using broadcasting communication.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: April 14, 1998
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering Inc.
    Inventors: Hiroshi Wataya, Hiroaki Nakanishi, Keijiro Hayashi, Yoshiaki Adachi, Hideki Tonooka, Kenji Matsuzaki, Tsutomu Onuki, Isao Terakado
  • Patent number: 5519875
    Abstract: A distributed processing system capable of realizing efficient management of a multiplicity of objects in a large scale distributed processing comprises an objectification unit which makes it possible to handle an assembly of objects as one object and a message transfer unit by which a request for a processing to one object provided by objectification by the objectification unit is made to an optimal one of plural objects subjected to objectification.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: May 21, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takanori Yokoyama, Masaru Shimada, Tadashi Kamiwaki, Masahiko Saito, Yoshiki Kobayashi, Hiroaki Nakanishi
  • Patent number: 5245193
    Abstract: A new method for forming on a substrate such micomechanics as a micro link mechanism by means of micromachining. The new method includes a process of implanting carbon ions to improve frictional properties of at least a slidable portion of the micromechanics formed. Micomechanics having their slidable portion made of a compound of silicon and such a dopant as carbon.
    Type: Grant
    Filed: April 10, 1991
    Date of Patent: September 14, 1993
    Assignee: Shimaduzu Corporation
    Inventor: Hiroaki Nakanishi
  • Patent number: 5149604
    Abstract: A battery accommodating structure for accommodating first and second batteries in such a way that they are fixed in its accommodating portions by two pressing plates different from each other. A moving member which allows the two different pressing plates to be detached is provided to move in response to the movement of a power switch of an appliance which uses the accommodating structure. When the moving member is located at a position where the power switch is turned on, it prevent both of the first and second batteries from being removed from the accommodating portions, but when it is located at another position where the power switch is turned off, it allows one of the first and second batteries to be removed from the corresponding accommodating portion.
    Type: Grant
    Filed: February 14, 1991
    Date of Patent: September 22, 1992
    Assignee: Casio Computer Co. Ltd.
    Inventor: Hiroaki Nakanishi
  • Patent number: 5082363
    Abstract: In a distance measuring apparatus for optically detecting a distance to an object by using a triangulation method, two signals which are obtained from a position sensitive device are added and it is detected that the result of the addition has exceeded a predetermined threshold level. On the other hand, it is assumed that a signal waveform to drive a light emitting device is a signal whose level increases with an elapse of time. When the addition result exceeds the threshold level, the level of the drive signal is held constant. At this time, by dividing a signal obtained from the position sensitive device by the signal indicative of the addition result, a signal relating to the distance to the object is obtained.
    Type: Grant
    Filed: December 12, 1990
    Date of Patent: January 21, 1992
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Hiroaki Nakanishi, Hidehiro Fukumoto, Kuniharu Shibata, Hidetoshi Matsumoto
  • Patent number: 4896258
    Abstract: A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.
    Type: Grant
    Filed: July 2, 1986
    Date of Patent: January 23, 1990
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hiroaki Nakanishi, Kenzi Hirose, Takao Kobayashi, Yoshihiro Miyazaki
  • Patent number: 4891601
    Abstract: In a multipole linear accelerator such as of a quadrupole type, fine positional adjustment of the tip portions of the electrodes constituting the multipole structure can be made with electric contact kept substantially unaffected between the electrodes and the cavity drum in which the electrodes are mounted. Each of the electrodes are provided with a series of contact plates on both sides of the root portion of the electrode over the whole length thereof. Each of the contact plates, which are held to the root portion of the electrode by means of an adjusting screw bolt, slantwise bridges the root portion of the electrode and the inner surface of the cavity drum with elastic contact pieces interposed.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: January 2, 1990
    Assignee: Shimadzu Corporation
    Inventors: Masatoshi Asari, Ikuo Konishi, Hiroyuki Fujita, Akira Hirakimoto, Hiroaki Nakanishi
  • Patent number: 4839846
    Abstract: An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).
    Type: Grant
    Filed: March 12, 1986
    Date of Patent: June 13, 1989
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi
  • Patent number: 4811269
    Abstract: A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.
    Type: Grant
    Filed: October 8, 1986
    Date of Patent: March 7, 1989
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi
  • Patent number: 4783731
    Abstract: A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: November 8, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Miyazaki, Jushi Ide, Takeshi Kato, Hiroaki Nakanishi, Tadaaki Bandoh
  • Patent number: 4563737
    Abstract: A virtual storage managing system in which the storage address is managed by means of a virtual address, and the virtual storage area which can be assigned by the virtual address is divided into an address non-translation area which does not require the address translation and an address translation system which requires an address translation. The address translation area is divided into an address fixed area and an address variable area. In the address translation area, the correspondence between the virtual address and the real address is fixed in a 1:1 fashion, whereas, in the address variable area, the correspondence is determined at the time of starting of execution of a program and is dismissed when the execution of the program is completed.
    Type: Grant
    Filed: December 9, 1982
    Date of Patent: January 7, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Tomoaki Nakamura, Keiichi Nakane, Hiroaki Nakanishi, Koji Hirai