Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: With regard to paired drive transistors, the shape of an active area is (point or line) symmetrical to a channel area in the vicinity of the channel area. With regard to paired transfer transistors, likewise, the shape of a word line is (point or line) symmetrical to the channel area in the vicinity thereof. With this structure, even if a gate electrode (word line) should be misaligned, therefore, the shapes of the channel areas of the paired transistors would become identical, so that there would be no difference between characteristics.

Abstract: Two intracell wiring serving as the gate electrodes of driver transistors and load transistors and arranged substantially parallel to each other between two word lines substantially parallel to each other so as to be perpendicular to the word lines are arranged as the first layer. Ground wiring and a power supply wiring are arranged as the second layer on the first layer through an insulating film. Each intracell wiring serves as the gate electrodes of one driver transistor and one load transistor and is connected to the drain regions of the other driver transistor and the other load transistor. The ground wiring are connected to the source regions of the driver transistors, and the power supply wiring is connected to the source regions of the load transistors.

Abstract: A contact hole connecting the source region of a LDD construction driver transistor and a grounding wiring layer (Vss) is provided in self-alignment with respect to a gate electrode of a driver transistor. With the source region formed by impurity introduced through the contact hole, the driver transistor is provided with asymmetric source/drain structure. By this, the on current of the LDD construction driver transistor can be improved without increasing the transistor size. Furthermore, imbalance of diffusion layer resistance in the source region can be reduced to improve stability of cell operation.