Abstract: In a semiconductor device including a semiconductor substrate, and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 ?m/?m2.

Abstract: A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: In a semiconductor integrated circuit device, a sheet-like temperature monitor member of vanadium oxide is provided, whose one end is connected to one via while the other end is connected to another via. A sheet-like thermal conducting layer of aluminum is provided below the temperature monitor member. A region equal to or greater than a half of the entire temperature monitor member overlies the thermal conducting layer in a plan view.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.

Abstract: On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Abstract: Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor. Since the areas defined by the loops forming these two inductors are equal to each other, the inductances of the inductors are also equal to each other. Between both the inductors, the lengths in the loop of the portions (the conductive layers 1a and 1b) formed on a lower interlayer insulating film are equal to each other, while the lengths in the loop of the portions (the conductive layers 2a and 2b) formed on an upper interlayer insulating film are also equal to each other. This allows external disturbances such as parasitic capacitance to affect both the inductors equally. Accordingly, a voltage controlled oscillator incorporating the invention can stably provide undistorted sinusoidal oscillation signals.

Abstract: A semiconductor substrate made of P? type or P?? type silicon having a thickness of approximately 700 ?m and a resistivity of 10 ?·cm to 1000 ?·cm is provided, a BOX layer with a thickness of 0.2 ?m to 10 ?m is provided on the semiconductor substrate and a p? type SOI layer is provided on this BOX layer. A first insulating film, which makes contact with the BOX layer, is locally buried in this p? type SOI layer and a CMOS is formed in a region of the p? type SOI layer wherein the above-described first insulating film is not provided. A second insulating film is provided above the first insulating film and over the CMOS, so as to cover the CMOS, and an inductor is provided on the region of this second insulating film corresponding to the first insulating film.

Abstract: In a semiconductor integrated circuit device, an integrated circuit portion is provided on a surface of a P-type silicon substrate and in a multilayer interconnection layer. The semiconductor integrated circuit device also includes a temperature sensor portion. At the higher level than the multilayer interconnection layer, a sheet member formed of vanadium oxide is provided. The sheet member and a resistor are connected in series between a ground potential wiring and a power-supply potential wiring, and an output terminal is connected to a connection point between the sheet member and the resistor.

Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.

Abstract: In a semiconductor integrated circuit device, an integrated circuit portion is provided on a surface of a P-type silicon substrate and in a multilayer interconnection layer. The semiconductor integrated circuit device also includes a temperature sensor portion. At the higher level than the multilayer interconnection layer, a sheet member formed of vanadium oxide is provided. The sheet member and a resistor are connected in series between a ground potential wiring and a power-supply potential wiring, and an output terminal is connected to a connection point between the sheet member and the resistor.

Abstract: A semiconductor device, in which four pieces of strip-shaped electrodes, whose longitudinal directions are the same, are formed in each layer of a plurality of wiring layers that are provided by a same design rule with each other, simultaneously with regular wirings. In each wiring layer, two pieces each of first electrode and second electrode are formed parallelly with each other, alternately, and remote from each other. Then, the first electrodes formed in each layer are connected to each other by a first via, the second electrodes formed in each layer are connected to each other by a second via, a first structure body formed by connecting the first electrodes and the first via to each other is connected to a ground wiring, and a second structure body formed by connecting the second electrodes and the second via to each other is connected to a power source wiring.

Abstract: A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.

Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Abstract: In a semiconductor integrated circuit, a P-type epitaxial layer is provided on the entire surface of a P-type bulk substrate. The resistivity of the P-type bulk substrate is set to 1000 &OHgr;·cm, and the thickness and the resistivity of the P-type epitaxial layer is set to 5 &mgr;m and 10 &OHgr;·cm, respectively. Then, a digital section and an analog section are provided remote from each other on the P-type epitaxial layer, where a digital circuit and an analog circuit are formed on the digital section and analog section, respectively. Further a device isolation region reaching the P-type bulk substrate is formed in a region between the digital section and analog section of the P-type epitaxial layer.

Abstract: An integrated circuit is manufactured by providing a P− or P−− type semiconductor substrate with a resistivity of 10 to 1000 &OHgr;·cm, disposing a CMOS on top of the semiconductor substrate, depositing an insulating film with several wirings embedded therein over the CMOS, and disposing an inductor on top of the insulating film in a region that is apart from where the CMOS is positioned. A p+ type diffused layer with a resistivity of about 0.01 &OHgr;·cm is disposed between the semiconductor substrate and the CMOS.

Abstract: Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

Abstract: A solid-state imaging device such as a CMOS image sensor includes photodiode portions that are designed for both improving sensitivity and reducing crosstalk of electrical charge to adjacent pixels. A p-type layer, which has an impurity concentration that is lower than that of a substrate p+-layer, is formed on the substrate p+-layer which is a p-type silicon semiconductor substrate of high impurity concentration. An n-type photoelectric conversion region is provided at a position on the upper side of the p-type layer. By means of this configuration, of the photoelectrons that are generated in the p-type layer, electrons that diffuse in the direction of the substrate are reliably captured in substrate p+-layer and annihilated by recombination.

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed, by which the sensitivity characteristics of the photodiode and the operation characteristics of the MOS transistor are improved and easy and low-cost manufacturing is realized. The CMOS image sensor comprises a photodiode having a light reception surface covered by a multi-layered antireflection film which is formed by alternately depositing two or more kinds of insulating films whose refractive indexes are different; and at least one MOS transistor having diffusion layers which respectively function as source and drain areas, wherein a silicide layer is formed on each diffusion layer. The photodiode and the MOS transistor are provided on a common substrate and are electrically connected with each other.