Abstract: Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor. Since the areas defined by the loops forming these two inductors are equal to each other, the inductances of the inductors are also equal to each other. Between both the inductors, the lengths in the loop of the portions (the conductive layers 1a and 1b) formed on a lower interlayer insulating film are equal to each other, while the lengths in the loop of the portions (the conductive layers 2a and 2b) formed on an upper interlayer insulating film are also equal to each other. This allows external disturbances such as parasitic capacitance to affect both the inductors equally. Accordingly, a voltage controlled oscillator incorporating the invention can stably provide undistorted sinusoidal oscillation signals.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: A semiconductor substrate made of P− type or P−− type silicon having a thickness of approximately 700 &mgr;m and a resistivity of 10 &OHgr;·cm to 1000 &OHgr;·cm is provided, a BOX layer with a thickness of 0.2 &mgr;m to 10 &mgr;m is provided on the semiconductor substrate and a p− type SOI layer is provided on this BOX layer. A first insulating film, which makes contact with the BOX layer, is locally buried in this p− type SOI layer and a CMOS is formed in a region of the p− type SOI layer wherein the above-described first insulating film is not provided. A second insulating film is provided above the first insulating film and over the CMOS, so as to cover the CMOS, and an inductor is provided on the region of this second insulating film corresponding to the first insulating film.

Abstract: An integrated circuit is manufactured by providing a P− or P−− type semiconductor substrate with a resistivity of 10 to 1000 &OHgr;·cm, disposing a CMOS on top of the semiconductor substrate, depositing an insulating film with several wirings embedded therein over the CMOS, and disposing an inductor on top of the insulating film in a region that is apart from where the CMOS is positioned. A p+ type diffused layer with a resistivity of about 0.01 &OHgr;·cm is disposed between the semiconductor substrate and the CMOS.

Abstract: The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Abstract: A DRAM includes a memory cell array section where a number of bit lines are located periodically and densely, and a peripheral circuit section formed at the outside of the memory cell array section and adjacent to the memory cell array section. A half of the bit lines formed in the memory cell array section are pulled out from the memory cell array section into the peripheral circuit section and are located periodically but sparsely in the peripheral circuit section. In the peripheral circuit section, the half of the bit lines have a portion which has a line width “B” larger than the line width “A” of the bit lines in the memory cell array section, and which is separated from the memory cell array section by a predetermined distance on the order of a minimum standardized size “D”. A line space “C” in the memory cell array section and the minimum standardized size “D” fulfill the relation of C≦D≦2×C.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: An image sensor is disclosed that prevents a photoelectrically-converted signal from being corrupted during a readout operation. The image sensor includes a line-selection line located on an upper side of a pixel relative to a top to bottom scan direction and disposed across the pixel in a direction substantially perpendicular to the top to bottom scanning direction. A signal reset line is located on a lower side of the pixel relative to a top to bottom scan direction and is disposed across the pixel in a direction substantially perpendicular to the top to bottom scanning direction. The line-selection line and the signal-reset line are disposed above and below a photoelectric conversion portion of the pixel.

Abstract: A DRAM includes a memory cell array section where a number of bit lines are located periodically and densely, and a peripheral circuit section formed at the outside of the memory cell array section and adjacent to the memory cell array section. A half of the bit lines formed in the memory cell array section are pulled out from the memory cell array section into the peripheral circuit section and are located periodically but sparsely in the peripheral circuit section. In the peripheral circuit section, the half of the bit lines have a portion which has a line width “B” larger than the line width “A” of the bit lines in the memory cell array section, and which is separated from the memory cell array section by a predetermined distance on the order of a minimum standardized size “D”. A line space “C” in the memory cell array section and the minimum standardized size “D” fulfill the relation of C≦D≦2×C.

Abstract: A solid-state imaging device such as a CMOS image sensor includes photodiode portions that are designed for both improving sensitivity and reducing crosstalk of electrical charge to adjacent pixels. A p-type layer, which has an impurity concentration that is lower than that of a substrate p+-layer, is formed on the substrate p+-layer which is a p-type silicon semiconductor substrate of high impurity concentration. An n-type photoelectric conversion region is provided at a position on the upper side of the p-type layer. By means of this configuration, of the photoelectrons that are generated in the p-type layer, electrons that diffuse in the direction of the substrate are reliably captured in substrate p+-layer and annihilated by recombination.

Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.

Abstract: The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed, by which the sensitivity characteristics of the photodiode and the operation characteristics of the MOS transistor are improved and easy and low-cost manufacturing is realized. The CMOS image sensor comprises a photodiode having a light reception surface covered by a multi-layered antireflection film which is formed by alternately depositing two or more kinds of insulating films whose refractive indexes are different; and at least one MOS transistor having diffusion layers which respectively function as source and drain areas, wherein a silicide layer is formed on each diffusion layer. The photodiode and the MOS transistor are provided on a common substrate and are electrically connected with each other.

Abstract: The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of the chip by the light, the signal electric charges are collected in a photo detective region and the photo detective region has a barrier diffusion layer adjacent thereto so as to collect the signal electric charges effectively. The above-mentioned structure of the solid state image pick-up device can provide superior features that the chip of the solid state image pick-up device is protected from the deterioration of elements included in the chip and the destruction of the elements by Electro Static Discharge, resulting in the reliability improvement of the chip.

Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

Abstract: According to a novel pattern layout of a full CMOS SRAM cell comprising first and second transfer, driver, and load transistors, six in total, the driver and load transistors are parallel to a buried word line. The first transfer transistor and the first driver transistor are alongside and parallel to one complementary data line and the second transfer transistor and the second driver transistor are alongside and parallel to the other complementary data line. Moreover, a power bus and a reference bus are parallel to and on both sides of each of the complementary data lines. Preferably, four gate electrodes of the first and second driver and load transistors are individually formed while the word line is used gate electrodes of the first and second transfer transistors.

Abstract: In a semiconductor device in which a source and a drain are formed on both sides of a buried gate provided in a trench, metal wires for the source and the drain are provided above the source and drain, via an intervening interlayer insulation film, a wire for a gate being provided so as to be sandwiched between the source and drain wires, this being formed on the same level of interconnect layers as the source and drain wires and being formed over the gate.

Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: In a method for manufacturing a semiconductor device, an anti-oxidation layer is formed on a semiconductor substrate of a first conductivity type. Then, a first photoresist pattern layer for defining an active area is formed on the anti-oxidation layer, and the anti-oxidation layer is etched by using the first photoresist pattern layer as a mask. Then, a second photoresist pattern layer is formed on a part of the first photoresist pattern layer. In this case, a width of the second photoresist pattern layer is larger than a width of the part of the first photoresist pattern layer. Then, ions of the first conductivity type are introduced into the semiconductor substrate by using the first and second photoresist pattern layers as a mask. Then, the semiconductor substrate is thermally oxidized by using the anti-oxidation layer as a mask to form a semiconductor oxide layer while activating the ions to form a channel stopper region below the semiconductor oxide layer.

Abstract: In a static memory cell including two load resistors connected to a power supply line, two cross-coupled drive transistors connected between the load resistors and two ground lines and two transfer transistors connected between the load resistors and two data lines, the data lines are in parallel with and do not cross over the power supply line and the ground lines.