Abstract: An exemplary aspect of the present invention is a memory card that includes: a memory that stores data; a driver that modulates the data stored in the memory; a transmitter that transmits the data modulated by the driver to a receiver provided in an external main unit; and an IC chip having the driver and the transmitter formed therein.

Abstract: A solid state imaging device having a light receiving region on a first surface side of a semiconductor substrate, incident light from an object to be imaged being illuminated on a second surface side of the semiconductor substrate, the solid state imaging device including an impurity diffusion layer formed on the first surface side of the semiconductor substrate, a surface of the impurity diffusion layer being silicided, and a gate electrode formed on the first surface side of the semiconductor substrate. The impurity diffusion layer includes the light receiving region disposed on the first surface side of the semiconductor substrate, a surface of the light receiving region being silicided, and the impurity diffusion layer includes at least a surface adjacent to the gate electrode.

Abstract: In a conventional solid state imaging device, there is a room for improvement in sensitivity. In order to solve the problem, a solid state imaging device includes a semiconductor substrate and a light receiving portion. The light receiving portion is provided adjacent to a surface layer on the surface (a first surface) side of the semiconductor substrate. The surface of the light receiving portion is silicided. The solid state imaging device is one in which light from an object to be imaged incident on the back side (a second surface) of the semiconductor substrate is photoelectric-converted inside the semiconductor substrate, the light receiving portion receives electric charge generated by the photoelectric conversion, and the above mentioned object to be imaged is imaged.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: A width of a region where each of the N wells is in contact with the buried P well is not more than 2 ?m. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.

Abstract: In a semiconductor device including a semiconductor substrate and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 ?A/?m2.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrate. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.

Abstract: In a semiconductor device including a semiconductor substrate, and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 ?A/?m2.

Abstract: The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a capacitive element formation region 20 of a semiconductor device 1, an N-type well 22 as a conductive layer is formed in a surface layer of a P-type semiconductor substrate 10. A capacitive film 24 is deposited on a front surface of the semiconductor substrate 10 on which the N-type well 22 is formed. The part of front surface of the semiconductor substrate 10 in which the capacitive film 24 is deposited is substantially flat. An upper electrode 26 is provided on the capacitive film 24. The upper electrode 26 constitutes a capacitive element (on-chip capacitor) together with the N-type well 22, located opposite the upper electrode 26 across the capacitive film 24.

Abstract: A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.

Abstract: On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Abstract: A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.

Abstract: Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.

Abstract: In a semiconductor integrated circuit device, a sheet-like temperature monitor member of vanadium oxide is provided, whose one end is connected to one via while the other end is connected to another via. A sheet-like thermal conducting layer of aluminum is provided below the temperature monitor member. A region equal to or greater than a half of the entire temperature monitor member overlies the thermal conducting layer in a plan view.

Abstract: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.