Patents by Inventor Hiroaki Yamashita

Hiroaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939667
    Abstract: A method for manufacturing a wavelength conversion member, includes: providing a wavelength conversion layer having a phosphor-containing portion and a light reflecting portion surrounding the phosphor-containing portion, and the wavelength conversion layer having an upper surface, a bottom surface and at least one side surface; forming a light-blocking film on the upper surface of the wavelength conversion layer; and removing a part of the light-blocking film by laser processing to expose at least a part of the phosphor-containing portion from the light-blocking film.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: March 26, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Naoki Eboshi, Hiroaki Yuto, Hiroki Sakata, Toshiaki Yamashita, Akinori Hara
  • Publication number: 20240098949
    Abstract: A cooling structure includes a flow path-forming member that forms a flow path for a refrigerant to pass through, wherein: the flow path-forming member includes, on a basal inner wall thereof, a cooling fin installation section provided with at least one cooling fin projecting from the basal inner wall toward an inner side of the flow path, the cooling fin installation section being disposed separately from side inner walls of the flow path-forming member; and the flow path-forming member includes, on a side inner wall thereof, at least one obstacle projecting from the side inner wall toward the inner side of the flow path.
    Type: Application
    Filed: January 17, 2022
    Publication date: March 21, 2024
    Inventors: Yuji FUKUKAWA, Takahiro YAMASHITA, Hiroaki SHODA
  • Patent number: 11933059
    Abstract: A method for reinforcing a concrete structure so as to have high substrate visibility and sufficient reinforcing performance. A fiber sheet for reinforcing a concrete structure, the sheet including: a framework in which a filament-based, multi-axial mesh sheet and a matrix resin are integrated, wherein the multi-axial mesh sheet has a base weight amount in a range of 500 g/m2 to 1000 g/m2.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: March 19, 2024
    Assignee: DENKA COMPANY LIMITED
    Inventors: Tomohiro Yamashita, Hiroaki Nishimura
  • Patent number: 11919579
    Abstract: A power supply system includes a system control unit, an auxiliary power supply, and an auxiliary-power-supply control unit. The system control unit and the auxiliary-power-supply control unit are configured such that information of at least one control unit of the system control unit and the auxiliary-power-supply control unit is able to be output to another control unit of the system control unit and the auxiliary-power-supply control unit. The at least one control unit is configured to output information indicating that an operation of the at least one control unit is stopped to the other control unit when the at least one control unit stops the operation of the at least one control unit.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 5, 2024
    Assignees: JTEKT CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kazuma Hasegawa, Toshihiro Takahashi, Yuji Fujita, Kenichi Abe, Yugo Nagashima, Yuuta Kajisawa, Takashi Koudai, Hiroaki Hanzawa, Atsushi Satou, Yosuke Yamashita, Shintaro Takayama, Tokuaki Hibino
  • Publication number: 20240039505
    Abstract: A piezoelectric resonator device according to one or more embodiments may be provided, in which a crystal resonator plate includes a cutout part between a vibrating part and an external frame part, and a metal film formed on a first main surface of a first sealing member is electrically connected to an external electrode terminal formed on a second main surface, which does not face an internal space, of a second sealing member via a first internal wiring formed on an inner wall surface of the external frame part.
    Type: Application
    Filed: December 13, 2021
    Publication date: February 1, 2024
    Applicant: DAISHINKU CORPORATION
    Inventors: Satoru ISHINO, Hiroaki YAMASHITA
  • Patent number: 11824509
    Abstract: When a thick frequency adjustment metal film of a tuning fork-type vibration piece is irradiated with a beam on a wafer for frequency coarse adjustment, projections are possibly formed on a roughened end of the frequency adjustment metal film. Such projections are pressurized and pushed down not to chip off under any impact, so that the risk of frequency fluctuations is suppressed.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: November 21, 2023
    Assignee: DAISHINKU CORPORATION
    Inventor: Hiroaki Yamashita
  • Patent number: 11756791
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
  • Patent number: 11621696
    Abstract: A tuning fork-type vibration piece is provided, in which a cushioning portion is formed on the base of a package and allowed to contact parts for contact of arm portions which are any parts but their edges, and the parts for contact of the arm portions that contact the cushioning portion are electrodeless regions, which prevents the risk of frequency fluctuations caused by any electrode being chipped off by contact with the cushioning portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 4, 2023
    Assignee: DAISHINKU CORPORATION
    Inventors: Tomo Fujii, Hiroaki Yamashita
  • Patent number: 11563413
    Abstract: When a thick frequency adjustment metal film of a tuning fork-type vibration piece is irradiated with a beam on a wafer for frequency coarse adjustment, projections are possibly formed on a roughened end of the frequency adjustment metal film. Such projections are pressurized and pushed down not to chip off under any impact, so that the risk of frequency fluctuations is suppressed.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 24, 2023
    Assignee: DAISHINKU CORPORATION
    Inventor: Hiroaki Yamashita
  • Publication number: 20220263492
    Abstract: When a thick frequency adjustment metal film of a tuning fork-type vibration piece is irradiated with a beam on a wafer for frequency coarse adjustment, projections are possibly formed on a roughened end of the frequency adjustment metal film. Such projections are pressurized and pushed down not to chip off under any impact, so that the risk of frequency fluctuations is suppressed.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 18, 2022
    Inventor: Hiroaki YAMASHITA
  • Publication number: 20220144649
    Abstract: A colloidal silica is disclosed that contains, with high purity, silica particles having an appropriate particle density, a high aggregation ratio, and a high alkoxy group content, and to provide a method for producing the colloidal silica in a simple manner at reduced costs. The colloidal silica containing silica particles is disclosed, wherein the silica particles have an average primary particle size of 33 nm or more, an aggregation ratio of 1.2 or more, and a particle density of 1.95 or more, the silica particles contain 1000 ppm by mass or more of alkoxy groups per gram of the silica particles, the proportion of the number of silica particles having an equivalent circle diameter under 20 nm is less than 15%, and the silica particles contain a primary amine in an amount of 5 ?mol or more per gram of the silica particles.
    Type: Application
    Filed: February 26, 2020
    Publication date: May 12, 2022
    Applicant: FUSO CHEMICAL CO., LTD.
    Inventors: Yuma Negishi, Hideki Otsuki, Hiroaki Yamashita, Toshiki Chiba
  • Publication number: 20220127150
    Abstract: Colloidal silica containing silica particles that have a small particle size (e.g., an average primary particle size of 20 nm or less) and that contain alkoxy groups, and a method for producing the colloidal silica, are disclosed. The colloidal silica containing silica particles can have a small particle size and exhibit a suppressed increase in the average secondary particle size after storage. The colloidal silica containing silica particles wherein the silica particles have an average primary particle size of 20 nm or less, the silica particles have a ratio (m/n) of the content of alkoxy groups m (ppm) to the average primary particle size n (nm) of 300 or more, the silica particles have a particle density of 1.95 or more, and the silica particles have an increase rate of average secondary particle size of 12% or less in a storage stability test.
    Type: Application
    Filed: February 26, 2020
    Publication date: April 28, 2022
    Applicant: FUSO CHEMICAL CO., LTD.
    Inventors: Hiroaki Yamashita, Yuma Shibuichi, Yuka Fujimura
  • Patent number: 11290082
    Abstract: Main surface electrodes formed on main surfaces on front and back sides of vibrating arms are electrically coupled via through electrodes formed in a stem portion so as to penetrate through front and back surfaces thereof. One of the main surface electrodes of the vibrating arm is electrically coupled to side surface electrodes through a routing wiring formed by way of a crotch part between roots of the vibrating arms, and the one of the main surface electrodes is further electrically coupled to the other one of the main surface electrodes through the side surface electrodes.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 29, 2022
    Assignee: DAISHTNKU CORPORATION
    Inventor: Hiroaki Yamashita
  • Patent number: 11239824
    Abstract: A tuning fork-type vibration piece is provided, in which a cushioning portion is formed on the base of a package to make contact with abutting portions of arm portions which are any parts but their edges, and the abutting portions of the arm portions allowed to contact the cushioning portion are electrodeless regions including no electrode, which prevents the risk of frequency fluctuations that may occur in case an electrode is chipped off by possible contact with the cushioning portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 1, 2022
    Assignee: Daishinku Corporation
    Inventors: Tomo Fujii, Hiroaki Yamashita
  • Publication number: 20210305049
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.
    Type: Application
    Filed: September 10, 2020
    Publication date: September 30, 2021
    Inventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
  • Patent number: 11075611
    Abstract: An object is to provide a frequency adjustment method for a piezoelectric resonator device that is applicable to a microminiaturized device and that can adjust the frequency without deteriorating the accuracy of frequency adjustment. A frequency adjustment method for a tuning-fork quartz resonator is applicable to a tuning-fork quartz resonator that includes a tuning-fork quartz resonator piece having a pair of resonator arms 31, 32 and metallic adjustment films W formed on the resonator arms. The frequency adjustment method adjusts the frequency by reduction of a mass of the metallic adjustment films W. The frequency adjustment method includes: a rough adjustment step for roughly adjusting the frequency by partially thinning or removing the metallic adjustment films W; and a fine adjustment step for finely adjusting the frequency by at least partially thinning or removing products W1, W2 derived from the metallic adjustment film W during the rough adjustment step.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 27, 2021
    Assignee: Daishinku Corporation
    Inventor: Hiroaki Yamashita
  • Patent number: 10818750
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Takafumi Koumoto
  • Publication number: 20200303495
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 24, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki YAMASHITA, Syotaro ONO, Hisao ICHIJO, Takafumi KOUMOTO
  • Patent number: 10749022
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro Ono, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10720523
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta