Patents by Inventor Hiroaki Yamashita

Hiroaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818599
    Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: October 27, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Hiroaki Niimi, Shariq Siddiqui, Tenko Yamashita
  • Patent number: 10818750
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Takafumi Koumoto
  • Patent number: 10804270
    Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20200307675
    Abstract: A steer-by-wire vehicle includes a steering actuator configured to turn a wheel and a reaction actuator configure to apply a torque to a steering wheel. An electronic control unit of a control apparatus for the vehicle is configured to execute normal steering control for turning the wheel and applying a reaction torque to the steering wheel according to a rotation of the steering wheel, and, when an activation condition including that the normal steering control is not needed is satisfied, execute rotation suppression control for suppressing the rotation of the steeling wheel without prohibiting the rotation of the steering wheel. Specifically, the electronic control unit is configured to, based on a steering speed or a steering torque, determine a rotation suppression torque for suppressing the rotation of the steering wheel, and control the reaction actuator such that the rotation suppression torque is applied to the steering wheel.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaharu Yamashita, Shintaro Takayama, Yosuke Yamashita, Hiroaki Hanzawa
  • Publication number: 20200303495
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 24, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki YAMASHITA, Syotaro ONO, Hisao ICHIJO, Takafumi KOUMOTO
  • Publication number: 20200280034
    Abstract: According to one embodiment, an electricity storage device includes a first box, a second box, a storage battery, and a flow path. The second box includes a side plate and is housed in the first box. The storage battery is disposed in the second box while being connected to the side plate. The flow path is configured to include the side plate of the second box inside the first box and outside the second box and vertically penetrates the first box.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 3, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Yasuyuki KITAZAWA, Mitsuyo YAMASHITA, Naoyuki KURISU, Hiroaki YOSHINARI
  • Patent number: 10759233
    Abstract: In the tire 2, fillers 10 are layered over clinches 8 in portions outward of a carcass 14 in the axial direction. A carcass ply 50 is turned up around cores 44. Turned-up portions 50a are disposed between the fillers 10 and apexes 46. Each clinch 8 has a maximum thickness Tcx that is measured along a line normal to an inner surface, in the axial direction, of the clinch 8. A ratio of a thickness Tf1 of the filler 10 to a sum of the thickness Tf1 and the thickness Tcx is greater than or equal to 0.1 and not greater than 0.6. A percentage of a complex elastic modulus E*f of the filler 10 relative to a complex elastic modulus E*a of the apex 46 is greater than or equal to 70% and not greater than 125%.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 1, 2020
    Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.
    Inventors: Tadao Matsumoto, Yasutaka Iwata, Kentaro Yagyu, Fumikazu Yamashita, Shingo Umekita, Yasuaki Kuniyasu, Hiroaki Ninomiya
  • Patent number: 10749022
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro Ono, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10720523
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Patent number: 10692868
    Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10685961
    Abstract: A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer. The ILD is formed over the spacer layer. The contact trench exposes a p-type source/drain region of the pFET and exposes an n-type source/drain region of the NFET. A gate stack is included within the spacer layer. A p-type alloyed layer is formed on top of the p-type source/drain region in the pFET and on top of the n-type source/drain region of the nFET. The p-type alloyed layer on top of the n-type source/drain region of the nFET is converted into a metallic alloyed layer. A metallic liner layer is formed in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET and on top of the metallic alloyed layer of the nFET.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Joseph S. Washington, Tenko Yamashita
  • Publication number: 20200153408
    Abstract: A tuning fork-type vibration piece is provided, in which a cushioning portion is formed on the base of a package and allowed to contact parts for contact of arm portions which are any parts but their edges, and the parts for contact of the arm portions that contact the cushioning portion are electrodeless regions, which prevents the risk of frequency fluctuations caused by any electrode being chipped off by contact with the cushioning portion.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 14, 2020
    Inventors: Tomo FUJII, Hiroaki YAMASHITA
  • Publication number: 20200144988
    Abstract: A tuning fork-type vibration piece is provided, in which a cushioning portion is formed on the base of a package to make contact with abutting portions of arm portions which are any parts but their edges, and the abutting portions of the arm portions allowed to contact the cushioning portion are electrodeless regions including no electrode, which prevents the risk of frequency fluctuations that may occur in case an electrode is chipped off by possible contact with the cushioning portion.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 7, 2020
    Inventors: Tomo FUJII, Hiroaki YAMASHITA
  • Patent number: 10643893
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita
  • Patent number: 10638908
    Abstract: The present invention is a method for manufacturing cleaning members obtained by cutting multi-layer webs formed by: spreading fiber bundles, the lengthwise directions of which are parallel to the direction in which said are conveyed; and layering together at least the spread and non-woven fabric strips. Said method includes a step in which, before spreading, two or more are joined together, forming one or more join sections. Said joins are performed by joining the back end (with respect to the conveyance direction) of one to the front end (with respect to the conveyance direction) of the next fiber bundle.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 5, 2020
    Assignee: UNICHARM CORPORATION
    Inventors: Hiroaki Goto, Takayuki Matsumoto, Shigetomo Takahashi, Yuji Yamashita
  • Patent number: 10643894
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Publication number: 20200119142
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Syotaro Ono, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10600777
    Abstract: A semiconductor device includes a semiconductor body, first to third electrodes provided on the semiconductor body, and a control electrode. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes first to sixth layers. The second layer of a second conductivity type is selectively provided between the first layer of a first conductivity type and the first electrode. The third layer of the first conductivity type is selectively provided between the second layer and the first electrode. The fourth layer of the second conductivity type is provided between the first layer and the second and third electrodes. The fifth layer of the first conductivity type is selectively provided in the fourth layer and electrically connected to the first electrode. The sixth layer of the first conductivity type is provided in the fourth layer, and electrically connected to the third electrode.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 24, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hisao Ichijo, Syotaro Ono, Hiroaki Yamashita
  • Publication number: 20200091335
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro ONO, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200083320
    Abstract: A semiconductor device includes a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first and second semiconductor layers are alternately arranged in a first direction along a front surface of the semiconductor body, and each include multiple portions arranged in a second direction directed from a back surface toward the front surface of the semiconductor body. The first and second semiconductor layers are configured such that, in an active region, a large/small relationship between amounts of the first conductivity type impurity and the second conductivity type impurity in the portions positioned at the same level in the second direction reverses at a center in the second direction of the second semiconductor layer, and in the terminal region, the large/small relationship reverses alternately in the portions arranged in the second direction.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 12, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Ohta, Syotaro Ono, Hideto Sugawara, Hisao Ichijo, Hiroaki Yamashita