Patents by Inventor Hiroaki Yamashita
Hiroaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130248979Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.Type: ApplicationFiled: September 11, 2012Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Masaru Izumisawa, Hiroshi Ohta, Hiroaki Yamashita
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Publication number: 20130248988Abstract: A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.Type: ApplicationFiled: September 8, 2012Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro ONO, Wataru Saito, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
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Publication number: 20130221426Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.Type: ApplicationFiled: August 31, 2012Publication date: August 29, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
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Patent number: 8482028Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.Type: GrantFiled: March 19, 2012Date of Patent: July 9, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20130082261Abstract: A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.Type: ApplicationFiled: September 12, 2012Publication date: April 4, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Syotaro ONO, Toshiyuki NAKA, Shunji TANIUCHI, Hiroaki YAMASHITA
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Publication number: 20120241817Abstract: According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a control electrode, a third semiconductor layer, first and second main electrodes. The second semiconductor layer is provided on the first semiconductor layer, and has a higher impurity concentration than the first semiconductor layer. The control electrode is provided inside a first trench with an insulating film interposed, the first trench reaching the first semiconductor layer from a front surface of the second semiconductor layer. The third semiconductor layer is provided inside a second trench and including SixGe1-x or SixGeyC1-x-y, the second trench reaching the first semiconductor layer from the front surface of the second semiconductor layer and being adjacent to the first trench with the second semiconductor layer interposed. The first main electrode is connected to the first semiconductor layer, and the second main electrode is connected to the third semiconductor layer.Type: ApplicationFiled: March 19, 2012Publication date: September 27, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: WATARU SAITO, SYOTARO ONO, TOSHIYUKI NAKA, SHUNJI TANIUCHI, MIHO WATANABE, HIROAKI YAMASHITA
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Publication number: 20120241847Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.Type: ApplicationFiled: March 19, 2012Publication date: September 27, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: WATARU SAITO, SYOTARO ONO, TOSHIYUKI NAKA, SHUNJI TANIUCHI, MIHO WATANABE, HIROAKI YAMASHITA
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Publication number: 20120217555Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.Type: ApplicationFiled: January 24, 2012Publication date: August 30, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20120074461Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.Type: ApplicationFiled: September 16, 2011Publication date: March 29, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro ONO, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20120068258Abstract: According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode.Type: ApplicationFiled: March 21, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Syotaro ONO, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20120056262Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench.Type: ApplicationFiled: March 18, 2011Publication date: March 8, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Syotaro Ono, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20120012929Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film.Type: ApplicationFiled: March 18, 2011Publication date: January 19, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAITO, Syotaro Ono, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Patent number: 7613603Abstract: An efficient audio coding device that quantizes and encodes digital audio signals with a reduced amount of computation. A spatial transform unit subjects samples of a given audio signal to a spatial transform, thus obtaining transform coefficients of the signal. With a representative value selected out of the transform coefficients of each subband, a quantization step size calculator estimates quantization noise and calculates, in an approximative way, a quantization step size of each subband from the estimated quantization noise, as well as from a masking power threshold determined from a psycho-acoustic model of the human auditory system. A quantizer then quantizes the transform coefficients, based on the calculated quantization step sizes, thereby producing quantized values of those coefficients. The quantization step sizes are also used by a scalefactor calculator to calculate common and individual scalefactors.Type: GrantFiled: November 10, 2005Date of Patent: November 3, 2009Assignee: Fujitsu LimitedInventor: Hiroaki Yamashita
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Patent number: 7267732Abstract: There is provided a method for manufacturing steel parts for an automotive automatic transmission in which a desired joint portion of each steel part is copper-brazed at a high temperature while chromium in an alloy steel for machine structural use forming the steel part for an automotive automatic transmission is kept in a reducing atmosphere and without removal of carbon, and the part is successively reheated continuously with the copper brazing by utilizing residual heat at the time of copper brazing, by which the temperature of the part is increased to perform quench hardening. In the above-described manufacturing method, the heating treatment for copper brazing of the part and the heating treatment for quenching thereof are connected to each other via an intermediate cooling treatment in which the temperature of the part is decreased to a temperature below the Ar1 point, and these heating treatments are performed in an atmosphere of a neutral gas such as nitrogen gas supplied into a graphite muffle.Type: GrantFiled: August 5, 2004Date of Patent: September 11, 2007Assignees: NSK-Warner K.K., Kanto Yakin Kabushiki KaishaInventors: Hideharu Tsukamoto, Katsutoshi Yoshizawa, Hiroaki Yamashita
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Patent number: 7234635Abstract: A transaction degradation processing method to decide available transactions of automated transaction apparatus easily executes transaction degradation processing for a plurality of automated transaction apparatus installations. An administration server is connected with a plurality of the automated transaction apparatus and performs transaction degradation processing for a plurality of installations of automated transaction apparatus by using a database. There is no longer a need for separately installing programs and tables in each of automated transaction apparatus installations, modification of the table specifications is facilitated, and program maintainability is improved.Type: GrantFiled: November 10, 2004Date of Patent: June 26, 2007Assignees: Fujitsu Limited, Fujitsu Frontech LimitedInventors: Shinichiro Tsuchiya, Satoshi Tomi, Hiroaki Yamashita, Shogo Kawabata, Tomohiro Kamimura
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Patent number: 7190674Abstract: In a packet scheduler, an arithmetic-operation controlling means designates output ports in a time-sharing manner and a parallel arithmetic operation means performs an arithmetic operation common with the queues of each designated output port to obtain packet output completion due times (evaluation factors) of the top packets of queues of each output port. Intra-port selecting means selects the evaluation factor of a packet that is to be preferentially output for each output port based on the result of the arithmetic operations. Then inter-port selecting means determines one to be most-preferentially output from the top packets selected based on the selected evaluation factors and the bandwidths for the output ports. Therefore, an apparatus for controlling packet output having such a packet scheduler can realize accurately control bandwidths of a plurality of queues, high-speed processing and the reduced size thereby being incorporated in hardware.Type: GrantFiled: October 25, 2002Date of Patent: March 13, 2007Assignee: Fujitsu LimitedInventors: Takahiro Kobayakawa, Hiroaki Yamashita
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Publication number: 20060074693Abstract: An efficient audio coding device that quantizes and encodes digital audio signals with a reduced amount of computation. A spatial transform unit subjects samples of a given audio signal to a spatial transform, thus obtaining transform coefficients of the signal. With a representative value selected out of the transform coefficients of each subband, a quantization step size calculator estimates quantization noise and calculates, in an approximative way, a quantization step size of each subband from the estimated quantization noise, as well as from a masking power threshold determined from a psycho-acoustic model of the human auditory system. A quantizer then quantizes the transform coefficients, based on the calculated quantization step sizes, thereby producing quantized values of those coefficients. The quantization step sizes are also used by a scalefactor calculator to calculate common and individual scalefactors.Type: ApplicationFiled: November 10, 2005Publication date: April 6, 2006Inventor: Hiroaki Yamashita
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Publication number: 20050199701Abstract: A transaction degradation processing method to decide available transactions of automated transaction apparatus easily executes transaction degradation processing for a plurality of automated transaction apparatus installations. An administration server is connected with a plurality of the automated transaction apparatus and performs transaction degradation processing for a plurality of installations of automated transaction apparatus by using a database. There is no longer a need for separately installing programs and tables in each of automated transaction apparatus installations, modification of the table specifications is facilitated, and program maintainability is improved.Type: ApplicationFiled: November 10, 2004Publication date: September 15, 2005Applicants: Fujitsu Limited, Fujitsu Frontech LimitedInventors: Shinichiro Tsuchiya, Satoshi Tomi, Hiroaki Yamashita, Shogo Kawabata, Tomohiro Kamimura
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Publication number: 20050028904Abstract: There is provided a method for manufacturing steel parts for an automotive automatic transmission in which a desired joint portion of each steel part is copper-brazed at a high temperature while chromium in an alloy steel for machine structural use forming the steel part for an automotive automatic transmission is kept in a reducing atmosphere and without removal of carbon, and the part is successively reheated continuously with the copper brazing by utilizing residual heat at the time of copper brazing, by which the temperature of the part is increased to perform quench hardening. In the above-described manufacturing method, the heating treatment for copper brazing of the part and the heating treatment for quenching thereof are connected to each other via an intermediate cooling treatment in which the temperature of the part is decreased to a temperature below the Ar1 point, and these heating treatments are performed in an atmosphere of a neutral gas such as nitrogen gas supplied into a graphite muffle.Type: ApplicationFiled: August 5, 2004Publication date: February 10, 2005Inventors: Hideharu Tsukamoto, Katsutoshi Yoshizawa, Hiroaki Yamashita
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Publication number: 20030202517Abstract: In a packet scheduler, an arithmetic-operation controlling means designates output ports in a time-sharing manner and a parallel arithmetic operation means performs an arithmetic operation common with the queues of each designated output port to obtain packet output completion due times (evaluation factors) of the top packets of queues of each output port. Intra-port selecting means selects the evaluation factor of a packet that is to be preferentially output for each output port based on the result of the arithmetic operations. Then inter-port selecting means determines one to be most-preferentially output from the top packets selected based on the selected evaluation factors and the bandwidths for the output ports. Therefore, an apparatus for controlling packet output having such a packet scheduler can realize accurately control bandwidths of a plurality of queues, high-speed processing and the reduced size thereby being incorporated in hardware.Type: ApplicationFiled: October 25, 2002Publication date: October 30, 2003Inventors: Takahiro Kobayakawa, Hiroaki Yamashita