Patents by Inventor Hirofumi Nakano

Hirofumi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060128659
    Abstract: A galactosamine derivative represented by the following formula (1): wherein R1, R2 and R5 each independently represents SO3? or H, and at least one of them represents SO3?; R3 represents H, acetyl or SO3?; R4 represents H, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkenyl group, a substituted or unsubstituted alkynyl group, a substituted or unsubstituted acyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted aralkyl group; X represents O, S, NH or CH2; and represents an ? bond or a ? bond, and a sulfotransferase inhibitor comprising the derivative.
    Type: Application
    Filed: July 10, 2003
    Publication date: June 15, 2006
    Inventors: Osami Habuchi, Hirofumi Nakano, Toshihiko Sawada, Sonoko Fujii, Shiori Ohtake
  • Publication number: 20050069999
    Abstract: The present invention provides SH3 domain binding inhibitors comprising, as an active ingredient, a non-peptide compound exhibiting SH3 domain binding inhibitory activity, a low molecular weight compound with molecular weight less than 750 which exhibit SH3 domain binding inhibitory activity, in particular, a compound represented by the general formula (I) or (II) described above, a cytochalsin, etc., or pharmaceutically acceptable salts thereof. The present invention also provides compounds represented by the general formula (Va), (Vb) or (VI) described above or pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: April 19, 2002
    Publication date: March 31, 2005
    Inventors: Sreenath Sharma, Noriko Matsushita, Katsuhiko Ando, Chitose Yoshida, Hirofumi Nakano, Tsutomu Agatsuma, Yutaka Kanda
  • Publication number: 20050000587
    Abstract: To provide an automatic air supply mechanism for a pneumatic tire which can automatically supply air to a pneumatic tire by rotation of the pneumatic tire with respect to an axle when the air pressure in the pneumatic tire becomes a prescribed value or lower. There is provided an axle 101 and a wheel body rotatable with respect to the axle 101. An automatic air supply mechanism 1 is provided on the wheel body. The automatic air supply mechanism 1 has a constant pressure maintaining section 2 and a compression section 3. The constant pressure maintaining section 2 is configured to maintain the air pressure therein at a constant value and connected to the pneumatic tire mounted on the wheel body 110 in air flow communication. The compression section 3 compresses air when the wheel body 110 is rotated with respect to the axle 101 and feeds the compressed air into the constant pressure maintaining section 2.
    Type: Application
    Filed: April 26, 2002
    Publication date: January 6, 2005
    Inventor: Hirofumi Nakano
  • Publication number: 20040259173
    Abstract: A method for determining a target protein of a medicament, which comprises a step of judging that a protein, showing an increase in protease sensitivity in the presence of a medicament, is the target protein of said medicament. For example, a target protein of a medicament can be selected from among proteins contained in a cell lysate, and the like.
    Type: Application
    Filed: July 28, 2004
    Publication date: December 23, 2004
    Inventors: Sreenath V. Sharma, Chitose Yoshida, Hirofumi Nakano
  • Patent number: 6603190
    Abstract: A semiconductor device having a plated heat sink (PHS) layer on the back surface, preventing a short circuit between a bonding wire, and a first metal layer. A method of making a semiconductor device including forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, and forming the first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Patent number: 6515920
    Abstract: A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: February 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirofumi Nakano, Atsushi Miyanishi, Sizuo Morizane
  • Publication number: 20020181045
    Abstract: In the WDM systems, the OSNR and the signal loss among the optical signals are substantially minimized at the receiving terminal to combat the SRS effects. An equal amount of the signal loss is expected for every span in the transmission path so that the optical amplifier gain tilt is not affected among a number of wavelength frequencies in the optical signal. This is accomplished by controlling the amplification process according to a feedback from the monitoring units for monitoring the optical signal.
    Type: Application
    Filed: February 13, 2002
    Publication date: December 5, 2002
    Inventors: Tetsuya Uda, Hiroshi Masuda, Hirofumi Nakano, Eita Miyasaka, Satoshi Asamizu
  • Publication number: 20020181061
    Abstract: Optical signal transmission is improved by reducing the variance in light output level and OSNR by adjusting optical signal intensity and gain tilt, taking SRS influence into consideration.
    Type: Application
    Filed: January 17, 2002
    Publication date: December 5, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tetsuya Uda, Shigehiro Takashima, Shigenori Hayase, Yoshimasa Kusano, Satoshi Asamizu, Hirofumi Nakano
  • Publication number: 20020110027
    Abstract: A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced.
    Type: Application
    Filed: October 5, 2001
    Publication date: August 15, 2002
    Inventors: Hirofumi Nakano, Atsushi Miyanishi, Sizuo Morizane
  • Publication number: 20020048903
    Abstract: A semiconductor device having a PHS layer on the back surface thereof, preventing from a short circuit between a bonding wire and a first metal layer. Forming catalyst layer on a bottom of a first separation groove formed in the front surface of a semiconductor substrate, forming the first metal layer selectively in the first separation groove by an electroless plating technique using the catalyst layer as a catalyst.
    Type: Application
    Filed: November 8, 2001
    Publication date: April 25, 2002
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Patent number: 6335265
    Abstract: A semiconductor device has a plated heat sink layer on the back surface, preventing a short-circuit between a bonding wire and a first metal layer. A method of making a semiconductor device includes forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, forming a first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: January 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Patent number: 6222286
    Abstract: In a stepping motor, stator yokes have a plurality of comb-tooth-shaped magnetic poles 5b, 6b, 7b and 8b in such a manner that the comb-tooth-shaped magnetic poles are opposed to each other coaxially to a rotor portion made from a permanent magnet magnetized to have multiple magnetic poles, and an excitation coil is fitted on the external circumference of the stator yokes and the excitation coil and the stator yokes are surrounded by a frame yoke. Each of the yokes is formed of an Fe—Cr alloy having a predetermined ferrite single-phase structure so that occurrence of eddy currents in an alternating-current magnetic field is suppressed.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: April 24, 2001
    Assignee: Nisshin Steel Co., Ltd.
    Inventors: Kazuyuki Watanabe, Hirofumi Nakano, Toshihiko Takemoto, Ryoji Hirota
  • Patent number: 6191819
    Abstract: Picture-taking apparatus having viewpoint detecting structure includes viewed-point detecting circuitry for detecting a viewed-point of an operator on a display screen. Area setting circuitry is provided for setting a predetermined processing area at the viewed-point detected by the view-point detecting circuitry. Display circuitry is provided for displaying a mark at a predetermined position on the display screen. Processing circuitry is provided for performing a predetermined function corresponding to the mark in response to a detection of the viewed-point being on a predetermined area including the display position of the mark. Control circuitry is provided for causing the area setting circuitry to inhibit displacement of the predetermined area and to freeze the predetermined area at a fixed position on the screen in the case that the display circuitry displays the mark on the display screen.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: February 20, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirofumi Nakano
  • Patent number: 6124892
    Abstract: A panhead device includes a base, a support mount which is movably supported by the base to place a camera thereon, a driving mechanism for driving the support mount in at least one of a panning direction and a tilting direction, a controller for controlling the driving mechanism to cause the support mount to be moved in a predetermined direction, and a clutch mechanism, disposed inside the driving mechanism, for transmitting and blocking a driving force.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: September 26, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirofumi Nakano
  • Patent number: 6018630
    Abstract: A finder apparatus in which a viewpoint detecting apparatus is built in a finder unit and a light emitting device and a photosensing device constructing the viewpoint detecting apparatus are arranged in a space which is formed by notching a part of an eyepiece.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: January 25, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Arai, Hirofumi Nakano
  • Patent number: 5990954
    Abstract: An electronic equipment having a viewpoint detection unit comprises an area display circuit for displaying a predetermined area on a screen, a viewpoint detector for detecting a viewpoint of an operator, a switching circuit for detecting whether the viewpoint of the operator detected by the viewpoint detector is within the area or not and switching the operation state of a predetermined function between a first state and a second state depending on the detection result, and a unit for changing a border line position of the area on the screen between when the operation state is shifted from the first state to the second state and when it is shifted from the second state to the first state.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: November 23, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Kobayashi, Hirofumi Nakano
  • Patent number: 5925641
    Abstract: The present invention relates to a farnesyltransferase inhibitor and an antitumor agent comprising, as an active ingredient, a piperazinedione derivative represented by formula (I): ##STR1## wherein R.sup.1 and R.sup.2 independently represent lower alkyl, lower alkoxyalkyl, substituted or unsubstituted aryl, or aralkyl; R.sup.3 and R.sup.4 independently represent mercapto, lower alkanoylthio, aroylthio, lower alkoxycarbonylthio, or aryloxycarbonylthio, or alternatively R.sup.3 and R.sup.4 are combined together to form disulfide; and R.sup.5 and R.sup.6 independently represent hydrogen, lower alkyl, lower alkoxyalkyl, hydroxyalkyl, lower alkanoyloxyalkyl, aroyloxyalkyl, aralkyloxyalkyl, or aralkyl.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: July 20, 1999
    Assignee: Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Yutaka Kanda, Yutaka Saitoh, Kazuhito Akasaka, Tamio Mizukami, Hirofumi Nakano
  • Patent number: 5869903
    Abstract: A semiconductor device includes a circuit substrate having a first surface on which a high-frequency circuit is located; a first metal layer disposed on a second surface of the circuit substrate; bump wirings on the first surface of the circuit substrate and electrically connected to the high-frequency circuit; a metal wall disposed on the first surface of the circuit substrate surrounding the high-frequency circuit; a wiring substrate having one surface on which substrate wirings corresponding to the bump wirings are located, the wiring substrate being disposed on the circuit substrate so that the substrate wirings are electrically connected to the bump wirings, and in contact with the metal wall, sealing a region including the high-frequency circuit; and a second metal layer disposed on a second surface of the wiring substrate. An electromagnetic shielding effect sufficient for use in a high-frequency circuit is obtained and fabricating cost is considerably reduced.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: February 9, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsunori Nakatani, Hirofumi Nakano
  • Patent number: 5857121
    Abstract: A camera includes an electronic viewfinder adapted to electrically display a photographing image, a visual line detection unit for detecting the position of a camera operator's visual line on a picture plane of the electronic viewfinder, and a display processing unit for displaying on the electronic viewfinder a photographing-related information involved in a camera photographing. In such a camera, the display processing unit controls a display position of the photographing-related information in accordance with an output of the visual line detection unit.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: January 5, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Arai, Hirofumi Nakano
  • Patent number: 5796132
    Abstract: On a semiconductor substrate with an active layer, a first-stage recess groove is formed by photolithography and wet or dry etching. On the semiconductor substrate and the surface of the first-stage recess groove, a surface passivation film a crystalline material such as i-GaAs or an insulating film of, e.g., SiON, is formed. The surface passivation film on an area where an ohmic electrodes is to be formed is removed and the ohmic electrode is formed on the area by vapor deposition. Thereafter, in the first-stage recess groove, a second-stage recess groove is formed by photolithography and wet or dry etching. A gate electrode is formed on the second-stage recess groove by sputtering or the like.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: August 18, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirofumi Nakano, Osamu Ishihara