Patents by Inventor Hirofumi Watatani

Hirofumi Watatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005627
    Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 7, 2021
    Inventors: Tatsuya HINOUE, Kengo KAJIWARA, Ryosuke ITOU, Naohiro HOSODA, Yohei MASAMORI, Kota FUNAYAMA, Keisuke TSUKAMOTO, Hirofumi WATATANI
  • Patent number: 9437606
    Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Johann Alsmeier, Yao-Sheng Lee, Masanori Terahara, Hirofumi Watatani, Jayavel Pachamuthu
  • Patent number: 9123728
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 1, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takahiro Kono, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
  • Patent number: 9099496
    Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 4, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Ming Tian, Jayavel Pachamuthu, Atsushi Suyama, James Kai, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien, Masanori Terahara, Hirofumi Watatani
  • Patent number: 9093480
    Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 28, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien, Masanori Terahara, Hirofumi Watatani
  • Publication number: 20150008503
    Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Raghuveer S. MAKALA, Johann ALSMEIER, Yao-Sheng LEE, Masanori TERAHARA, Hirofumi WATATANI, Jayavel PACHAMUTHU
  • Publication number: 20140367762
    Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: Ming Tian, Jayavel Pachamuthu, Atsushi Suyama, James Kai, Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien, Masanori Terahara, Hirofumi Watatani
  • Publication number: 20140295636
    Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 2, 2014
    Applicant: SanDisk Technologies, Inc.
    Inventors: Raghuveer S. Makala, Yao-Sheng Lee, Johann Alsmeier, Henry Chien, Masanori Terahara, Hirofumi Watatani
  • Publication number: 20140131873
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Application
    Filed: January 22, 2014
    Publication date: May 15, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takahiro Kouno, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
  • Patent number: 8669177
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiro Kouno, Shinichi Akiyama, Hirofumi Watatani, Tamotsu Owada
  • Publication number: 20130330912
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
  • Patent number: 8604552
    Abstract: A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Hirofumi Watatani
  • Patent number: 8536708
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Patent number: 8349722
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
  • Publication number: 20120326315
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Patent number: 8338953
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Publication number: 20120322272
    Abstract: A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.
    Type: Application
    Filed: August 29, 2012
    Publication date: December 20, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tamotsu Owada, Hirofumi Watatani
  • Publication number: 20120252227
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
  • Patent number: 8105935
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: January 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoki Ohara, Hirofumi Watatani, Tamotsu Owada, Kenichi Yanai
  • Publication number: 20110241211
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Hisaya SAKAI, Hirofumi WATATANI, Kazuya OKUBO