Patents by Inventor Hirofumi Watatani

Hirofumi Watatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8030207
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Patent number: 7951686
    Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: May 31, 2011
    Assignee: Fujitsu Limited
    Inventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
  • Patent number: 7749897
    Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama
  • Publication number: 20100144117
    Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.
    Type: Application
    Filed: February 18, 2010
    Publication date: June 10, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
  • Patent number: 7701016
    Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: April 20, 2010
    Assignee: Fujitsu Limited
    Inventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
  • Publication number: 20100012991
    Abstract: A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.
    Type: Application
    Filed: September 28, 2009
    Publication date: January 21, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tamotsu OWADA, Hirofumi Watatani
  • Patent number: 7642185
    Abstract: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic. On the hydrophilic surface of the first film, a second film is formed which is an insulating film made of a low dielectric constant insulating material having a relative dielectric constant of 2.7 or smaller or an insulating film made by a coating method. A sufficient adhesion property is obtained when a film made of low dielectric constant insulating material is formed on an insulating film made of silicon carbide having a small amount of oxygen contents.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: January 5, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tamotsu Owada, Hirofumi Watatani, Ken Sugimoto, Shun-ichi Fukuyama
  • Publication number: 20090278259
    Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.
    Type: Application
    Filed: February 5, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Takahiro KOUNO, Shinichi AKIYAMA, Hirofumi WATATANI, Tamotsu OWADA
  • Publication number: 20090149031
    Abstract: The present invention provides a semiconductor device that can restrict the dissolution hindering phenomenon in a chemically amplified resist film. More specifically, after the formation of a contact pattern on a semiconductor substrate, a wiring pattern is formed on the contact pattern. A SiC film, a first SiOC film, a SiC film, a second SiOC film, a USG film as a diffusion preventing film, and a silicon nitride film as a reflection preventing film, are formed on the wiring pattern. A dual damascene structure is then formed using the chemically amplified resist film and another chemically amplified resist film. In this manner, the N2 gas generated during the formation of the silicon nitride film as a reflection preventing film can be prevented from diffusing into the second SiOC film formed under the silicon nitride film. Accordingly, the reaction of the N2 gas with the H group contained in the second SiOC film and the generation of an amine group such as NH in the second SiOC film can be prevented.
    Type: Application
    Filed: October 23, 2008
    Publication date: June 11, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Katsumi Kakamu, Hirofumi Watatani, Masanobu Ikeda
  • Patent number: 7541296
    Abstract: Disclosed is a method for effectively forming a Low-k insulating film. The method comprises the steps of: spin-coating on an underlying layer a precursor solution formed by dispersing Low-k materials in a solvent to form a coating film, subjecting the coating film to a baking treatment under heating for about several minutes at a temperature near a boiling point of the solvent, forming, on the coating film after the baking treatment, an SiC barrier film using a CVD method, and subjecting the coating film to a hydrogen plasma treatment through the barrier film continuously using the same CVD apparatus as used in forming the barrier film without taking out the coating film from the CVD apparatus.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: June 2, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tamotsu Owada, Hirofumi Watatani, Yoshihiro Nakata, Shirou Ozaki, Shun-ichi Fukuyama
  • Publication number: 20090093130
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Application
    Filed: December 3, 2008
    Publication date: April 9, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
  • Patent number: 7485570
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: February 3, 2009
    Assignee: Fujitsu Limited
    Inventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
  • Publication number: 20080305645
    Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.
    Type: Application
    Filed: July 18, 2008
    Publication date: December 11, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama
  • Publication number: 20080284027
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Application
    Filed: April 28, 2008
    Publication date: November 20, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Shinichi AKIYAMA, Kazuo KAWAMURA, Hisaya SAKAI, Hirofumi WATATANI, Kazuya OKUBO
  • Publication number: 20080233734
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Naoki OHARA, Hirofumi WATATANI, Tamotsu OWADA, Kenichi YANAI
  • Publication number: 20080057717
    Abstract: A semiconductor device manufacturing method that includes depositing a first insulating film on a semiconductor substrate, etching a part of the first insulating film, and performing UV irradiation to the first insulating film.
    Type: Application
    Filed: August 23, 2007
    Publication date: March 6, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tamotsu OWADA, Hirofumi WATATANI, Shirou OZAKI, Hisaya SAKAI, Kenichi YANAI, Naoki OHARA, Tadahiro IMADA, Yoshihiro NAKATA
  • Publication number: 20070228488
    Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.
    Type: Application
    Filed: October 3, 2006
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
  • Publication number: 20070181966
    Abstract: A method of fabricating a semiconductor device comprises the steps of forming an isolation trench in a semiconductor substrate, depositing a silicon oxide film on the semiconductor substrate by a high-density plasma CVD process such that the silicon oxide film fills the isolation trench and such that the silicon oxide film contains water with such an amount that there is caused a shrinkage in the silicon oxide film when a dehydration process is applied to the silicon oxide film, causing a shrinkage in the silicon oxide film by dehydrating the silicon oxide film, and removing the silicon oxide film deposited on the silicon substrate by a chemical mechanical polishing process.
    Type: Application
    Filed: May 19, 2006
    Publication date: August 9, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hirofumi Watatani, Ken Sugimoto
  • Publication number: 20070173054
    Abstract: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic. On the hydrophilic surface of the first film, a second film is formed which is an insulating film made of a low dielectric constant insulating material having a relative dielectric constant of 2.7 or smaller or an insulating film made by a coating method. A sufficient adhesion property is obtained when a film made of low dielectric constant insulating material is formed on an insulating film made of silicon carbide having a small amount of oxygen contents.
    Type: Application
    Filed: March 15, 2007
    Publication date: July 26, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Tamotsu Owada, Hirofumi Watatani, Ken Sugimoto, Shun-ichi Fukuyama
  • Publication number: 20070123035
    Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.
    Type: Application
    Filed: February 22, 2006
    Publication date: May 31, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama