Abstract: A low temperature film deposition process fills fine gaps while avoiding removal of the deposited film in post-processes, and is applicable to formation of semiconductor devices having both sparse and dense patterned regions, such as a combined logic and memory hybrid semiconductor device. A thermal CVD (chemical vapor deposition) method is performed at a first pressure to form a first insulation film on a main surface of a substrate having patterned recesses therein and, after the recesses are substantially filled, a second thermal CVD process is performed under a second pressure, lower than the first pressure and without interruption of the supply of the film forming gas during the transition from the first to the second process, thereby to form an insulation film continuously and without a barrier layer therebetween.

Abstract: A semiconductor device has a multilayer interconnection structure including a lower organic interlayer insulation film, an etching stopper film on the lower interlayer insulation film and an upper organic interlayer insulation film covering the etching stopper film, wherein the upper organic interlayer insulation film is covered by first and second etching stopper films of respective, different compositions.

Abstract: A low temperature film deposition process fills fine gaps while avoiding removal of the deposited film in post-processes, and is applicable to formation of semiconductor devices having both sparse and dense patterned regions, such as a combined logic and memory hybrid semiconductor device. A thermal CVD (chemical vapor deposition) method is performed at a first pressure to form a first insulation film on a main surface of a substrate having patterned recesses therein and, after the recesses are substantially filled, a second thermal CVD process is performed under a second pressure, lower than the first pressure and without interruption of the supply of the film forming gas during the transition from the first to the second process, thereby to form an insulation film continuously and without a barrier layer therebetween.

Abstract: A semiconductor device has a multilayer interconnection structure including a lower organic interlayer insulation film, an etching stopper film on the lower interlayer insulation film and an upper organic interlayer insulation film covering the etching stopper film, wherein the upper organic interlayer insulation film is covered by first and second etching stopper films of respective, different compositions.

Abstract: A method of making a semiconductor device has a multilayer interconnection structure including a lower organic interlayer insulation film, an etching stopper film on the lower interlayer insulation film and an upper organic interlayer insulation film covering the etching stopper film, wherein the upper organic interlayer insulation film is covered by first and second etching stopper films of respective, different compositions.

Abstract: An insulation structure is formed in a high-density plasma environment by depositing a first SiO.sub.2 film containing a substantial amount of F without a substrate bias, followed by depositing a second SiO.sub.2 film containing a reduced amount of F with a substantial substrate bias, and further followed by depositing a third SiO.sub.2 film containing a substantial amount of F without a substrate bias.

Abstract: A cleaning of a plasma chamber is done by a NF.sub.3 plasma treatment (typically under 1 to 1.5 Torr). The etching rate of an oxide layer can be improved by inserting, between the NF.sub.3 plasma treatments, a low pressure (lower than 10.sup.-1 Torr) plasma treatment preferably in a plasma of oxygen, water vapor, silane, fluorine, a hydrate compound, nitrogen trifluoride, or a mixture of nitrogen trifluoride with at least one of hydrogen fluoride, fluorine, water vapor and hydride compounds.