Patents by Inventor Hirokazu Honda

Hirokazu Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7217999
    Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 15, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Publication number: 20070020907
    Abstract: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.
    Type: Application
    Filed: September 15, 2006
    Publication date: January 25, 2007
    Inventors: Shinichi Miyazaki, Hirokazu Honda, Kenji Ooyachi
  • Publication number: 20060283625
    Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.
    Type: Application
    Filed: June 15, 2006
    Publication date: December 21, 2006
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
  • Publication number: 20060283629
    Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.
    Type: Application
    Filed: June 9, 2006
    Publication date: December 21, 2006
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 7138064
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. In the method, an etching-back layer consisting of aluminum or copper is formed on a base substrate and a multilayer wiring board is manufactured on the etching-back layer. After that the etching-back layer is etched to be removed under the condition that the multilayer wiring board and the base substrate are not etched, so that the base substrate is separated from the multilayer wiring board. Accordingly, the base substrate can be reused.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 21, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Publication number: 20060189125
    Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.
    Type: Application
    Filed: April 26, 2006
    Publication date: August 24, 2006
    Inventors: Keiichiro Kata, Hirokazu Honda, Kazuhiro Baba, Tadanori Shimoto, Katsumi Kikuchi, Rokuro Kambe, Satoshi Hirano, Shinya Miyamoto
  • Patent number: 7074650
    Abstract: In a flip-chip type semiconductor device, a pad electrode and a passivation film are formed on a semiconductor substrate. An insulating resin layer is formed on the passivation film, and an opening is formed above the electrode. A pad electrode adhesive metal film is formed on the substrate like a re-wiring pattern, and a plating feed layer metal film and a Cu plating layer are sequentially formed on the metal film to form a wiring layer. A metal post electrode is formed on the wiring layer. A solder bump is formed on the post electrodes, a support plate in which holes each having a diameter larger than the diameter of the solder bump are formed at positions adjusted to the solder bumps is arranged, and an insulating resin layer is formed between the support plate and the semiconductor substrate. Therefore, a stress acting on the solder bump is moderated.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: July 11, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Patent number: 7060604
    Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: June 13, 2006
    Assignees: NGK Spark Plug Co., Ltd., NEC Electronics Corporation
    Inventors: Keiichiro Kata, Hirokazu Honda, Kazuhiro Baba, Tadanori Shimoto, Katsumi Kikuchi, Rokuro Kambe, Satoshi Hirano, Shinya Miyamoto
  • Publication number: 20060012029
    Abstract: A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 19, 2006
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Hirokazu Honda, Koji Soejima, Shinichi Miyazaki
  • Publication number: 20060012048
    Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
    Type: Application
    Filed: July 6, 2005
    Publication date: January 19, 2006
    Inventors: Hideya Murai, Tadanori Shimoto, Takuo Funaya, Katsumi Kikuchi, Shintaro Yamamichi, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata, Kouji Matsui, Shinichi Miyazaki
  • Publication number: 20050252682
    Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D-65/D150)?3.0 (5) H23?140 (6) (H-65/H150)?2.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 17, 2005
    Inventors: Tadanori Shimoto, Katsumi Kikuchi, Hideya Murai, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata
  • Publication number: 20040169287
    Abstract: In a flip-chip type semiconductor device, a pad electrode and a passivation film are formed on a semiconductor substrate. An insulating resin layer is formed on the passivation film, and an opening is formed above the electrode. A pad electrode adhesive metal film is formed on the substrate like a re-wiring pattern, and a plating feed layer metal film and a Cu plating layer are sequentially formed on the metal film to form a wiring layer. A metal post electrode is formed on the wiring layer. A solder bump is formed on the post electrodes, a support plate in which holes each having a diameter larger than the diameter of the solder bump are formed at positions adjusted to the solder bumps is arranged, and an insulating resin layer is formed between the support plate and the semiconductor substrate. Therefore, a stress acting on the solder bump is moderated.
    Type: Application
    Filed: January 21, 2004
    Publication date: September 2, 2004
    Inventor: Hirokazu Honda
  • Publication number: 20040154163
    Abstract: A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the resist post being exposed. The exposed resist post is then removed by developing processing or the like, thus forming a through hole. A conductor is then embedded in the through hole by plating, thus forming a connecting conductor, and wirings are formed. A method of forming the connecting conductor does not impart damage to the semiconductor chip.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 12, 2004
    Inventors: Shinichi Miyazaki, Hirokazu Honda, Kenji Ooyachi
  • Publication number: 20040150118
    Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first -resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 5, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Patent number: 6767761
    Abstract: In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is formed on the semiconductor substrate and has openings corresponding to the pad electrodes. A plurality of flexible conductive members are filled in the openings. A plurality of metal bumps are formed on the flexible conductive layers.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 27, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Publication number: 20040089470
    Abstract: A printed circuit board is provided including a lower interconnect, a base insulating film formed on the lower interconnect, and a via hole formed on the base insulating film, and an upper interconnect connected to the lower interconnect with the via hole. The base insulating film has a thickness of about 3 to 100 &mgr;m and has a breaking strength of about 80 MPa or more at a temperature of 23° C. and when the base insulating film is defined to have a breaking strength “a” at a temperature of −65° C. and a breaking strength “b” at a temperature of 150° C., a value of a ratio (a/b) is about 4.5 or less.
    Type: Application
    Filed: November 6, 2003
    Publication date: May 13, 2004
    Applicant: NEC CORPORATION
    Inventors: Tadanori Shimoto, Hirokazu Honda, Keiichiro Kata, Hideya Murai, Katsumi Kikuchi, Kazuhiro Baba
  • Patent number: 6734566
    Abstract: In a flip-chip type semiconductor device, a pad electrode and a passivation film are formed on a semiconductor substrate. An insulating resin layer is formed on the passivation film, and an opening is formed above the electrode. A pad electrode adhesive metal film is formed on the substrate like a re-wiring pattern, and a plating feed layer metal film and a Cu plating layer are sequentially formed on the metal film to form a wiring layer. A metal post electrode is formed on the wiring layer. A solder bump is formed on the post electrodes, a support plate in which holes each having a diameter larger than the diameter of the solder bump are formed at positions adjusted to the solder bumps is arranged, and an insulating resin layer is formed between the support plate and the semiconductor substrate. Therefore, a stress acting on the solder bump is moderated.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: May 11, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Publication number: 20040082101
    Abstract: In a flip-chip type semiconductor device, a plurality of pad electrodes are formed on a semiconductor substrate. An insulating stress-absorbing resin layer made of thermosetting resin is formed on the semiconductor substrate and has openings corresponding to the pad electrodes. A plurality of flexible conductive members are filled in the openings. A plurality of metal bumps are formed on the flexible conductive layers.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Patent number: 6723627
    Abstract: There is provided a method for manufacturing semiconductor devices includes the steps of: packaging onto a wiring board a semiconductor chip that flux is coated to its right face onto which ball-like solder electrodes are connected; forcedly spraying a washing solution to an under-fill portion between the semiconductor chip and the wiring board, to wash off the flux; and exposing the wiring board to an oxygen-plasma atmosphere to conduct plasma processing on the wiring board.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: April 20, 2004
    Assignee: NEC Corporation
    Inventors: Syuuichi Kariyazaki, Hirokazu Honda
  • Publication number: 20040053489
    Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.
    Type: Application
    Filed: June 5, 2003
    Publication date: March 18, 2004
    Applicants: NGK SPARK PLUG CO., LTD., NEC ELECTRONICS CORPORATION
    Inventors: Keiichiro Kata, Hirokazu Honda, Kazuhiro Baba, Tadanori Shimoto, Katsumi Kikuchi, Rokuro Kambe, Satoshi Hirano, Shinya Miyamoto