Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

Abstract: The present disclosure relates to a Lactobacillus paracasei strain having polyamine production promoting activity in an organism, as well as its application and relevant technologies. The present disclosure also relates to the use of the Lactobacillus paracasei strain to promote polyamine production in humans and animals, which may be used, for instance, to reduce hepatic neutral fat. The present disclosure also relates to the use of the Lactobacillus paracasei strain as an agent to prevent or treat a disease, including fatty liver, non-alcoholic steatohepatitis, and liver cirrhosis.

Abstract: A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code.

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

Abstract: Provided is a plasticizing agent capable of plasticizing a biodegradable resin and imparting heat resistance to a molded article thereof. Specially, the plasticizing agent is a plasticizing agent for biodegradable resins, which is a polyester represented by the following formula (1) or formula (2) (In the formulae (1) and (2), B11 represents an aliphatic monocarboxylic acid residue having 7 to 20 carbon atoms; B12 represents an aliphatic monocarboxylic acid residue having 7 to 20 carbon atoms; B21 represents an aliphatic monoalcohol residue having 6 to 10 carbon atoms; B22 represents an aliphatic monoalcohol residue having 6 to 10 carbon atoms; G represents an alkylene glycol residue having 3 to 10 carbon atoms or an oxyalkylene glycol residue having 3 to 10 carbon atoms; A represents an alkylene dicarboxylic acid residue having 6 to 12 carbon atoms; and m and n each represent the number of repeating units enclosed in parentheses.

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

Abstract: An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

Abstract: A chip resistor capable of achieving both high specific resistance, a low TCR is provided. A chip resistor includes: an insulating substrate; a resistive layer formed of an alloy containing Cr, Si, and N, the resistive layer being provided on the insulating substrate; and a first high-nitrogen-containing layer provided on the resistive layer, the first high-nitrogen-containing layer being made of an alloy having a N atomic percentage higher than a N atomic percentage of the resistive layer.

Abstract: A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

Abstract: A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code. An execution circuit is configured to receive the control code from the instruction decoder and access a memory and generate an arithmetic result according to the control code.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

Abstract: A plasticizer composition for a vinyl chloride resin which can impart an excellent plasticization property and cold resistance to a vinyl chloride resin plastisol and is excellent in a non-bleeding property is provided. Specifically, a plasticizer composition for a vinyl chloride resin including an aliphatic diester (A) of an aliphatic dicarboxylic acid having 2 to 12 carbon atoms and an aliphatic monoalcohol having 4 to 18 carbon atoms, an aromatic diester (B) of an aromatic monocarboxylic acid having 6 to 12 carbon atoms and a glycol having 2 to 12 carbon atoms, and a phthalate (C), in which aliphatic diester (A):aromatic diester (B)=65:35 to 95:5 (mass ratio) is satisfied and (aliphatic diester (A)+aromatic diester (B)):phthalate (C)=5:95 to 35:65 (mass ratio) is satisfied.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

Abstract: The battery system includes a secondary battery, a voltage sensor, a current sensor, a temperature sensor, and a processor. The processor is configured to calculate a polarization overvoltage by subtracting a voltage drop amount caused by a DC resistance and a reactive resistance of the secondary battery determined in accordance with a temperature and an SOC of the secondary battery from a voltage difference between OCV and CCV of the secondary battery.

Abstract: A control device for a vehicle includes: a processor for performing control for autonomously parking the vehicle to a target position; and a storage unit storing a program necessary for travel control of the vehicle. As the control, the processor performs first control for starting movement of the vehicle to the target position in a state where a user of the vehicle is not in the vehicle, and second control for starting movement of the vehicle to the target position in a state where the user is in the vehicle, the processor updates the program, after a power of the vehicle is turned off and the processor executes the first control or the second control, and a start condition for updating the program is set more strictly when the first control is executed than when the second control is executed.