Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

Abstract: Provided is a plasticizer which can impart excellent heat resistance to a molded article of a vinyl chloride resin composition. Specifically, provided is a plasticizer for vinyl chloride resin, wherein the plasticizer is a polyester represented by the following formula (1) or (2), wherein, in the formulae (1) and (2), B11 represents an aliphatic monocarboxylic acid residue having 7 to 20 carbon atoms, B12 represents an aliphatic monocarboxylic acid residue having 7 to 20 carbon atoms, B21 represents an aliphatic monoalcohol residue having 6 to 10 carbon atoms, B22 represents an aliphatic monoalcohol residue having 6 to 10 carbon atoms, G represents an alkylene glycol residue having 3 to 10 carbon atoms or an oxyalkylene glycol residue having 3 to 10 carbon atoms, A represents an alkylenedicarboxylic acid residue having 6 to 12 carbon atoms, and each of m and n represents the number of repeating units in parentheses.

Abstract: According to the present invention, there is provided a polishing composition used for polishing a gallium compound-based semiconductor substrate. The polishing composition includes a silica abrasive; a compound Cpho having a phosphoric acid group or a phosphonic acid group; and water. In addition, according to the present invention, there is provided a method for polishing a gallium compound-based semiconductor substrate. The method includes a first polishing step in which polishing is performed using a slurry S1 containing an abrasive A1 and water; and a second polishing step in which polishing is performed using a slurry S2 containing an abrasive A2 and water, in this order. The abrasive A2 contains a silica abrasive. The slurry S2 further contains a compound Cpho having a phosphoric acid group or a phosphonic acid group.

Abstract: The present disclosure provides an exhaust gas purification catalyst having an improved Rh activation, which comprises a substrate and a catalyst coat layer formed on the substrate, the catalyst coat layer having a two-layer structure, wherein the catalyst coat layer includes an upstream portion on an upstream side and a downstream portion on a downstream side in an exhaust gas flow direction, and a part or all of the upstream portion is formed on a part of the downstream portion, wherein the upstream portion contains Rh fine particles and Pt, wherein the Rh fine particles have an average particle size measured by a transmission electron microscope observation of 1.0 nm or more to 2.0 nm or less, and a standard deviation ? of the particle size of 0.8 nm or less, and wherein the downstream portion contains Rh.

Abstract: A memory device is disclosed. The memory device includes at least one reference cell and multiple sense amplifiers. The at least one reference cell having a first terminal coupled to a ground. Each of the sense amplifiers has a first terminal and a second terminal. The first terminal is coupled to one of multiple first data lines, and the second terminal is coupled to a second terminal of the at least one reference cell.

Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

Abstract: A body-size class specification device of the present invention comprises a class feature-quantity information memorizing section to memorize class feature-quantity information to correlate plural classes for classifying a body size according to a dimension ratio of prescribed parts of a body with plural prescribed feature quantities for characterizing the plural classes, a first input section as an example of a feature-quantity acquiring section to acquire feature quantity of an object person to be specified for the class, an eye-height measuring section and an upper-body-length-ratio processing section, and a class specifying section to specify the class corresponding to the feature quantity of the object person acquired by the feature-quantity acquiring section based on the class feature-quantity information memorized by the class feature-quantity information memorizing section.

Abstract: The present invention further provides a composition for inhibiting purine body absorption, a composition for inhibiting purine nucleotide metabolism, a composition for inhibiting phosphatase, a composition for inhibiting uric acid level elevation, a composition for improving blood pressure, a composition for improving blood glucose level, a composition for improving liver function, a composition for controlling serum iron level, or a composition for promoting calcium absorption, comprising an inositol phosphate or a salt thereof. The present invention further provides a composition comprising an inositol phosphate or a salt thereof, wherein the taste thereof is improved by adding thereto a predetermined amount of calcium lactate.

Abstract: Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

Abstract: Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.

Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.