Patents by Inventor Hiroki Noguchi

Hiroki Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272606
    Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. the first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.
    Type: Application
    Filed: July 9, 2020
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Publication number: 20210271417
    Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
    Type: Application
    Filed: August 5, 2020
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih, Yih Wang
  • Publication number: 20210271479
    Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not.
    Type: Application
    Filed: July 8, 2020
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroki Noguchi, Yih Wang
  • Publication number: 20210272609
    Abstract: Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.
    Type: Application
    Filed: December 11, 2020
    Publication date: September 2, 2021
    Inventor: Hiroki Noguchi
  • Publication number: 20210272647
    Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
    Type: Application
    Filed: December 22, 2020
    Publication date: September 2, 2021
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Patent number: 11107530
    Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Perng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu
  • Publication number: 20210265002
    Abstract: A memory system is disclosed. The memory system includes a first memory array, an error correction code circuit, and a monitor circuit. The error correction code circuit is configured to receive data from the first memory array to correct, at least one error bit in the received data. The error correction code circuit is further configured to generate an error determination signal. The monitor circuit is coupled to the error correction code circuit. The monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.
    Type: Application
    Filed: September 3, 2020
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hiroki NOGUCHI
  • Publication number: 20210264970
    Abstract: A memory system is disclosed. The memory system includes a memory array and a controller. The controller is configured to perform a refresh operation to the memory array with a first refresh cycle rate. The first refresh cycle rate is derived from a first refresh time in a lookup table. The lookup table is configured to store refresh times and refresh temperatures corresponding to the refresh times separately.
    Type: Application
    Filed: August 18, 2020
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hiroki NOGUCHI, Yih WANG
  • Publication number: 20210201997
    Abstract: Disclosed herein are related to an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Perng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu
  • Publication number: 20210202827
    Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: MingYuan SONG, Shy-Jay LIN, William J. GALLAGHER, Hiroki NOGUCHI
  • Publication number: 20210201998
    Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 1, 2021
    Inventors: Perng-Fei Yuh, Jui-Che Tsai, Hiroki Noguchi, Yih Wang
  • Publication number: 20210177876
    Abstract: The present invention further provides a composition for inhibiting purine body absorption, a composition for inhibiting purine nucleotide metabolism, a composition for inhibiting phosphatase, a composition for inhibiting uric acid level elevation, a composition for improving blood pressure, a composition for improving blood glucose level, a composition for improving liver function, a composition for controlling serum iron level, or a composition for promoting calcium absorption, comprising an inositol phosphate or a salt thereof. The present invention further provides a composition comprising an inositol phosphate or a salt thereof, wherein the taste thereof is improved by adding thereto a predetermined amount of calcium lactate.
    Type: Application
    Filed: October 26, 2017
    Publication date: June 17, 2021
    Applicant: OTSUKA PHARMACEUTICAL CO., LTD.
    Inventors: Takeshi IKENAGA, Hiroki NOGUCHI, Chieko KOHASHI, Noriyuki KOUDA, Ayako TAKAISHI
  • Publication number: 20210174854
    Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Inventors: Win-San Khwa, Hiroki Noguchi, Ku-Feng Lin
  • Publication number: 20210134333
    Abstract: A memory device is disclosed in the present disclosure. The memory device includes multiple memory cells, multiple reference cells, and multiple sense amplifiers. The memory cells are coupled to first inputs of the sense amplifiers, respectively. The reference cells are coupled to second inputs of the sense amplifiers, respectively. The reference cells are coupled to each other.
    Type: Application
    Filed: July 30, 2020
    Publication date: May 6, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ku-Feng LIN, Hiroki NOGUCHI
  • Publication number: 20210134882
    Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Shy-Jay Lin, MingYuan Song, Hiroki Noguchi
  • Patent number: 10943667
    Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei-Chang Zhao
  • Patent number: 10642685
    Abstract: A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 5, 2020
    Assignee: Kioxia Corporation
    Inventors: Kazutaka Ikegami, Shinobu Fujita, Hiroki Noguchi
  • Publication number: 20200135288
    Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 30, 2020
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei-Chang Zhao
  • Publication number: 20200104205
    Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
    Type: Application
    Filed: August 8, 2019
    Publication date: April 2, 2020
    Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win San Khwa
  • Patent number: 10592163
    Abstract: A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Noguchi, Shinobu Fujita