Patents by Inventor Hiroki Ohara
Hiroki Ohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120179Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: December 17, 2024Publication date: April 10, 2025Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Publication number: 20250105964Abstract: A terminal includes: a reception unit configured to receive, in downlink, a reference signal for positioning without using a measurement gap during a reference signal processing period; and a control unit configured to assume that the reference signal is to be transmitted by using a duplex method during the reference signal processing period.Type: ApplicationFiled: February 4, 2022Publication date: March 27, 2025Applicant: NTT DOCOMO, INC.Inventors: Kousuke Shima, Hiroki Harada, Daisuke Kurita, Mayuki Okano, Masaya Okamura, Tomoya Ohara
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Publication number: 20250106665Abstract: A wireless relay device includes: a relay unit configured to relay a first wireless signal from a base station to a terminal; and a control unit configured to control relaying of the first wireless signal from the base station to the terminal. The control unit performs measurement of the first wireless signal and determines power amplification and a spatial domain filter to be applied to the relaying of the first wireless signal from the base station to the terminal based on a result of the measurement.Type: ApplicationFiled: January 28, 2022Publication date: March 27, 2025Applicant: NTT DOCOMO, INC.Inventors: Hiroki Harada, Daisuke Kurita, Mayuko Okano, Kousuke Shima, Masaya Okamura, Tomoya Ohara, Jing Wang, Weiqi Sun
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Publication number: 20250097917Abstract: A terminal according to one aspect of the present disclosure includes a receiving section that receives first configuration information related to use of a frequency to which shared spectrum channel access is applied, and second configuration information for configuring a resource in which frequency division multiplexing of a downlink (DL) resource and an uplink (UL) resource is available, and a control section that controls, based on the first configuration information and the second configuration information, use of the resource in which the frequency division multiplexing is available in the frequency applied with the shared spectrum channel access. According to one aspect of the present disclosure, it is possible to enhance efficiency of resource use.Type: ApplicationFiled: January 14, 2022Publication date: March 20, 2025Applicant: NTT DOCOMO, INC.Inventors: Hiroki Harada, Daisuke Kurita, Mayuko Okano, Kousuke Shima, Masaya Okamura, Tomoya Ohara
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Patent number: 12256438Abstract: A terminal includes a receiver that receives an index specifying configuration information for transmitting a random access preamble; and a controller that configures, in response to the receiver receiving additional information that specifies a time domain resource for transmitting the random access preamble, the time domain resource specified by the additional information, the time domain resource being configured by replacing a time domain resource for transmitting the random access preamble included in the configuration information specified by the index with the time domain resource specified by the additional information.Type: GrantFiled: July 9, 2019Date of Patent: March 18, 2025Assignee: NTT DOCOMO, INC.Inventors: Hideaki Takahashi, Akihito Hanaki, Hiroki Harada, Tomoya Ohara
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Publication number: 20250088331Abstract: A terminal includes: a transmission unit configured to transmit, in uplink, a reference signal for positioning; and a control unit configured to assume that resources of the reference signal for positioning are to be non-contiguously allocated.Type: ApplicationFiled: January 27, 2022Publication date: March 13, 2025Applicant: NTT DOCOMO, INC.Inventors: Masaya Okamura, Tomoya Ohara, Kousuke Shima, Hiroki Harada, Daisuke Kurita, Mayuko Okano
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Publication number: 20250062121Abstract: An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film.Type: ApplicationFiled: November 1, 2024Publication date: February 20, 2025Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
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Patent number: 12225558Abstract: A terminal includes a reception unit that receives, from a base station, a first set including a plurality of resources that include at least a synchronization signal and optionally further include a broadcast channel and a second set including a plurality of resources that include at least a synchronization signal added to the first set in a frequency domain and optionally further include a broadcast channel, a control unit that assumes a Quasi co location (QCL) identical to a QCL assumed for the first set when receiving the second set, and a communication unit that executes a random access procedure with the base station based on information included in the resources.Type: GrantFiled: September 5, 2019Date of Patent: February 11, 2025Assignee: NTT DOCOMO, INC.Inventors: Daiki Takeda, Tomoya Ohara, Hiroki Harada
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Patent number: 12219611Abstract: A terminal includes a reception unit that receives, from a base station, a set including a plurality of first resources that include at least a synchronization signal and optionally further include a broadcast channel, a control unit that determines which of the first resources included in the set is to be used based on a reception quality controlled for each of the first resources, and a communication unit that executes a random access procedure with the base station based on information included in the determined first resource.Type: GrantFiled: September 5, 2019Date of Patent: February 4, 2025Assignee: NTT DOCOMO, INC.Inventors: Daiki Takeda, Tomoya Ohara, Hiroki Harada
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Patent number: 12209321Abstract: To provide a method and an apparatus for producing a sodium hypochlorite solution on-site at a high efficiency and at the initial cost and suppressing operating cost without any problems about impurities derived from raw material water and raw salt. A method of producing a sodium hypochlorite solution on-site in the vicinity of a physical plant where a sodium hypochlorite solution is used.Type: GrantFiled: March 16, 2022Date of Patent: January 28, 2025Assignee: DE NORA PERMELEC LTDInventors: Hiroki Domon, Masahiro Ohara, Masaaki Kato
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Patent number: 12183743Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: August 9, 2023Date of Patent: December 31, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Publication number: 20240258119Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: ApplicationFiled: February 8, 2024Publication date: August 1, 2024Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroki OHARA
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Patent number: 12048185Abstract: The display device includes: a display area; a first peripheral area disposed outside the display area; a second peripheral area disposed outside the first peripheral area; an inner dam disposed in the first peripheral area; an outer dam disposed outside the inner dam in the first peripheral area; a resin part formed between the inner dam and the outer dam so as to be higher than the inner dam and the outer dam; and a sealing film disposed so as to overlap with the display area in a plan view. An outer edge of the sealing film overlaps with the resin part or the outer dam in a plan view.Type: GrantFiled: February 26, 2021Date of Patent: July 23, 2024Assignee: JAPAN DISPLAY INC.Inventor: Hiroki Ohara
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Patent number: 11937448Abstract: An electronic device is provided and includes first region including organic layer in light emitting element; nitride layers over organic layer; first organic insulating layer over organic layer; and second region including nitride layers, outside first region, wherein second region does not include organic layer and first organic insulating layer, wherein nitride layers include first, second and third nitride layers, wherein first nitride layer is between organic layer and first organic insulating layer in first region, wherein second and third nitride layers are over first nitride layer, and wherein second nitride layer is in contact with first organic insulating layer in first region.Type: GrantFiled: September 30, 2022Date of Patent: March 19, 2024Assignee: Japan Display Inc.Inventors: Hiroki Ohara, Akinori Kamiya
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Patent number: 11923204Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: GrantFiled: September 14, 2022Date of Patent: March 5, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
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Patent number: 11855194Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.Type: GrantFiled: October 13, 2021Date of Patent: December 26, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Miyuki Hosoba, Kosei Noda, Hiroki Ohara, Toshinari Sasaki, Junichiro Sakata
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Publication number: 20230387276Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: ApplicationFiled: June 27, 2023Publication date: November 30, 2023Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
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Publication number: 20230387136Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 11765931Abstract: A display device includes a first substrate, a display region with pixels each including a light emitting element above the first substrate, a first inorganic insulating layer covering the display region, a first organic insulating layer on the first inorganic insulating layer, a second inorganic insulating layer on the first organic insulating layer, a second organic insulating layer on the second inorganic insulating layer, a third organic insulating layer a on the second organic insulating layer, acidity of the third organic insulating layer being stronger than acidity of the second organic insulating layer, and a polarizing plate arranged on the third organic insulating layer.Type: GrantFiled: September 13, 2021Date of Patent: September 19, 2023Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Patent number: 11728350Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: February 16, 2022Date of Patent: August 15, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara