Patents by Inventor Hiroki Ohara
Hiroki Ohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230387276Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: ApplicationFiled: June 27, 2023Publication date: November 30, 2023Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
-
Publication number: 20230387136Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
-
Patent number: 11765931Abstract: A display device includes a first substrate, a display region with pixels each including a light emitting element above the first substrate, a first inorganic insulating layer covering the display region, a first organic insulating layer on the first inorganic insulating layer, a second inorganic insulating layer on the first organic insulating layer, a second organic insulating layer on the second inorganic insulating layer, a third organic insulating layer a on the second organic insulating layer, acidity of the third organic insulating layer being stronger than acidity of the second organic insulating layer, and a polarizing plate arranged on the third organic insulating layer.Type: GrantFiled: September 13, 2021Date of Patent: September 19, 2023Assignee: Japan Display Inc.Inventor: Hiroki Ohara
-
Patent number: 11728350Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: February 16, 2022Date of Patent: August 15, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
-
Patent number: 11683952Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.Type: GrantFiled: June 28, 2021Date of Patent: June 20, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisao Ikeda, Hiroki Ohara, Makoto Hosoba, Junichiro Sakata, Shunichi Ito
-
Patent number: 11665945Abstract: Disclosed is a display device including: a substrate; a first insulating film over the substrate, the first insulating film exposing a part of the substrate to provide an exposed surface to the substrate; a second insulating film in contact with the exposed surface and a first side surface of the first insulating film; and a first wiring over the second insulating film and in contact with the exposed surface, the first insulating film, and the second insulating film. The display device may further possess a third insulating film spaced from the second insulating film and in contact with the exposed surface. The first insulating film has a second side surface opposing the first side surface through the exposed surface. The third insulating film may be in contact with the second side surface, and the wiring may be located over and in contact with the third insulating film.Type: GrantFiled: August 19, 2021Date of Patent: May 30, 2023Assignee: Japan Display Inc.Inventor: Hiroki Ohara
-
Publication number: 20230022872Abstract: An electronic device is provided and includes first region including organic layer in light emitting element; nitride layers over organic layer; first organic insulating layer over organic layer; and second region including nitride layers, outside first region, wherein second region does not include organic layer and first organic insulating layer, wherein nitride layers include first, second and third nitride layers, wherein first nitride layer is between organic layer and first organic insulating layer in first region, wherein second and third nitride layers are over first nitride layer, and wherein second nitride layer is in contact with first organic insulating layer in first region.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Inventors: Hiroki OHARA, Akinori KAMIYA
-
Publication number: 20230019824Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: ApplicationFiled: September 14, 2022Publication date: January 19, 2023Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroki OHARA
-
Publication number: 20220384622Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
-
Patent number: 11462715Abstract: A display device in one embodiment according to the present invention includes a first region including a light emitting layer, a first nitride insulating layer over the light emitting layer, a first organic insulating layer over the first nitride insulating layer, a second nitride insulating layer over the first organic insulating layer, and a third nitride insulating layer over the second nitride insulating layer. The second nitride insulating layer is in contact with the first organic insulating layer and the third nitride insulating layer. An absolute value of a stress of the second nitride insulating layer is greater than or equal to an absolute value of a stress of the first nitride insulating layer and less than an absolute value of a stress of the third nitride insulating layer.Type: GrantFiled: August 27, 2020Date of Patent: October 4, 2022Assignee: Japan Display Inc.Inventors: Hiroki Ohara, Akinori Kamiya
-
Patent number: 11456187Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: GrantFiled: July 2, 2020Date of Patent: September 27, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
-
Publication number: 20220300889Abstract: Provided is a work management apparatus including: a display control unit configured to display on a display apparatus a permit to work for a work package, which is a work unit for constructing a construction object; a registration unit configured to register one or more workers in the work package; a first acquisition unit configured to acquire work duration information indicating a work duration that has been required to complete the work package; a generation unit configured to generate work record information including identification information on the work package and the work duration information; and an output unit configured to output the work record information.Type: ApplicationFiled: October 1, 2019Publication date: September 22, 2022Applicant: JGC CORPORATIONInventors: Erio OOSATO, Kazuyuki KOJIMA, Hiroki OHARA
-
Publication number: 20220277268Abstract: Provided is a project management apparatus configured to manage a project of constructing a construction object, the project management apparatus including: a display control unit configured to display on a display apparatus a simulation model of the construction object a reception unit configured to receive an operation of a user; a setting unit configured to set an order of a plurality of work packages, which are work units for constructing the construction object, based on an operation of the user on the simulation model; and a generation unit configured to generate a schedule of the project based on the order.Type: ApplicationFiled: October 1, 2019Publication date: September 1, 2022Applicant: JGC CORPORATIONInventors: Kazuyuki KOJIMA, Hiroki OHARA, Ming YU, Erio OOSATO
-
Publication number: 20220270006Abstract: Provided is a work management apparatus including: a reception unit configured to receive an operation of a user; a generation unit configured to generate an image showing a state of the work by making a composite of a first layer including a drawing of the construction object and a second layer selected by an operation of the user from a plurality of second layers in which the work is to be registered; a display control unit configured to display the image on a display apparatus; and an editing unit configured to edit the second layer in accordance with an operation of the user when it is determined that the user has an editing permission set to the second layer.Type: ApplicationFiled: October 1, 2019Publication date: August 25, 2022Applicant: JGC CORPORATIONInventors: Ming YU, Kazuyuki KOJIMA, Hiroki OHARA
-
Patent number: 11417754Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: GrantFiled: September 21, 2020Date of Patent: August 16, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
-
Publication number: 20220181359Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. Au oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: February 16, 2022Publication date: June 9, 2022Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
-
Patent number: 11348949Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: August 20, 2020Date of Patent: May 31, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
-
Publication number: 20220037153Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.Type: ApplicationFiled: October 13, 2021Publication date: February 3, 2022Inventors: Shunpei YAMAZAKI, Miyuki HOSOBA, Kosei NODA, Hiroki OHARA, Toshinari SASAKI, Junichiro SAKATA
-
Publication number: 20210408483Abstract: A display device includes a first substrate, a display region with pixels each including a light emitting element above the first substrate, a first inorganic insulating layer covering the display region, a first organic insulating layer on the first inorganic insulating layer, a second inorganic insulating layer on the first organic insulating layer, a second organic insulating layer on the second inorganic insulating layer, a third organic insulating layer a on the second organic insulating layer, acidity of the third organic insulating layer being stronger than acidity of the second organic insulating layer, and a polarizing plate arranged on the third organic insulating layer.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Inventor: Hiroki OHARA
-
Publication number: 20210384286Abstract: Disclosed is a display device including: a substrate; a first insulating film over the substrate, the first insulating film exposing a part of the substrate to provide an exposed surface to the substrate; a second insulating film in contact with the exposed surface and a first side surface of the first insulating film; and a first wiring over the second insulating film and in contact with the exposed surface, the first insulating film, and the second insulating film. The display device may further possess a third insulating film spaced from the second insulating film and in contact with the exposed surface. The first insulating film has a second side surface opposing the first side surface through the exposed surface. The third insulating film may be in contact with the second side surface, and the wiring may be located over and in contact with the third insulating film.Type: ApplicationFiled: August 19, 2021Publication date: December 9, 2021Inventor: Hiroki OHARA