Patents by Inventor Hiroki Ohara
Hiroki Ohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200090950Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hiroki OHARA
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Patent number: 10566408Abstract: Provided is a highly reliable display device that does not easily cause a wiring or an interlayer insulating layer to be cracked when being folded. A display device includes a flexible substrate; a plurality of pixels arrayed on the substrate; and a wiring, provided on the substrate, transmitting a signal to drive the plurality of pixels. The wiring includes a first conductive layer having an opening pattern at least in a partial area thereof.Type: GrantFiled: August 21, 2018Date of Patent: February 18, 2020Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Publication number: 20200052003Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: ApplicationFiled: August 21, 2019Publication date: February 13, 2020Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 10559643Abstract: A display device, including a display region formed of a plurality of pixels, and a terminal region formed on an outer side of the display region, includes a terminal wiring formed in the terminal region, a pixel wiring formed in each of the plurality of pixels, an insulating film, which is formed in the terminal region on an upper layer of the terminal wiring, and is formed in the display region on an upper layer of the pixel wiring, and a preventing film formed in the terminal region on an upper layer of the insulating film. The terminal wiring is exposed in an electrical connection region of the terminal region.Type: GrantFiled: November 16, 2016Date of Patent: February 11, 2020Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Patent number: 10497769Abstract: A display device includes a plurality of pixels arranged in a first direction and a second direction intersecting the first direction, a first wiring extending along a pixel arranged in the first direction among the plurality of pixels, and a second wiring extending along a pixel arranged in the second direction intersecting the first direction among the plurality of pixels, wherein at least of the first wiring and the second wiring includes a first conducting layer arranged contacting an insulating surface, a second conducting layer arranged above the first conducting layer, and a third conducting layer arranged contacting an upper surface and side surface of the second conducting layer and contacting a side surface of the first conducting layer, an end part of the third conducting layer being arranged on the insulating surface.Type: GrantFiled: December 20, 2017Date of Patent: December 3, 2019Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Publication number: 20190363192Abstract: A semiconductor device includes an oxide semiconductor layer above an insulating surface, a source electrode in contact with a side surface of the oxide semiconductor layer, a drain electrode in contact with a side surface of the oxide semiconductor layer, a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode, and, a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film. The gate electrode is arranged above and outside of the source electrode and the drain electrode.Type: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Inventor: Hiroki OHARA
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Patent number: 10490420Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: GrantFiled: September 13, 2018Date of Patent: November 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
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Publication number: 20190348285Abstract: An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film.Type: ApplicationFiled: July 23, 2019Publication date: November 14, 2019Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
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Publication number: 20190305117Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: ApplicationFiled: April 16, 2019Publication date: October 3, 2019Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
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Patent number: 10424675Abstract: A semiconductor device includes an oxide semiconductor layer above an insulating surface, a source electrode in contact with a side surface of the oxide semiconductor layer, a drain electrode in contact with a side surface of the oxide semiconductor layer, a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode, and, a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film. The gate electrode is arranged above and outside of the source electrode and the drain electrode.Type: GrantFiled: January 16, 2018Date of Patent: September 24, 2019Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Patent number: 10418467Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: GrantFiled: April 16, 2018Date of Patent: September 17, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
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Patent number: 10411039Abstract: Provided is a semiconductor device including: a first transistor over a substrate, the first transistor having a gate electrode, an oxide semiconductor film, and a gate insulating film between the gate electrode and the oxide semiconductor film; an insulating film over the first transistor, the insulating film having a first film and a second film over the first film; and a terminal electrically connected to the oxide semiconductor film through an opening portion in the insulating film. The insulating film has a first region in contact with the terminal, and the first region has an oxygen composition larger than that in another region of the insulating film.Type: GrantFiled: June 25, 2018Date of Patent: September 10, 2019Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Patent number: 10396097Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: October 6, 2017Date of Patent: August 27, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Patent number: 10332996Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: GrantFiled: December 3, 2015Date of Patent: June 25, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
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Patent number: 10332743Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer.Type: GrantFiled: August 1, 2017Date of Patent: June 25, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
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Patent number: 10283627Abstract: An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method.Type: GrantFiled: July 10, 2014Date of Patent: May 7, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Hiroki Ohara, Junichiro Sakata
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Patent number: 10274767Abstract: There is provided a display device including a flexible substrate having a first surface and a second surface opposite to the first surface, the substrate including a display region on the first surface and a bending region on a part of the first surface or on a part of the second surface, the display region being arranged with a plurality of pixels, the bending region including an uneven pattern alternately arranged with regions, the thickness of the substrate being different in each region; and a plurality of wirings transmitting a signal for driving the plurality of pixels, each of the plurality of wirings being arranged in a top part or a bottom part of a convex portion in the uneven pattern in the bending region.Type: GrantFiled: July 14, 2017Date of Patent: April 30, 2019Assignee: Japan Display Inc.Inventor: Hiroki Ohara
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Patent number: 10269941Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.Type: GrantFiled: April 16, 2018Date of Patent: April 23, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
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Patent number: 10229936Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.Type: GrantFiled: October 6, 2017Date of Patent: March 12, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
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Publication number: 20190035641Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.Type: ApplicationFiled: October 1, 2018Publication date: January 31, 2019Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI