Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.

Abstract: An electrode material has a solid concentration of 72% or more. It includes a composite particle, a sulfide solid electrolyte, and a solvent. The composite particle includes an active material and a fluoride solid electrolyte. The fluoride solid electrolyte covers at least part of a surface of the active material. The sulfide solid electrolyte is adhered to the composite particle.

Abstract: An electrode includes an active material layer. The active material layer includes a composite particle and an imidazoline-based compound. The composite particle includes a core particle and a covering layer. The covering layer covers at least part of a surface of the core particle. The core particle includes an active material. The covering layer includes a first layer and a second layer. At least part of the first layer is interposed between the core particle and the second layer. The first layer includes a first solid electrolyte. The second layer includes a second solid electrolyte. The first solid electrolyte is a fluoride. The second solid electrolyte is a sulfide.

Abstract: An electrode material comprises a composite particle. The composite particle includes a core particle and a covering layer. The covering layer covers at least part of a surface of the core particle. The core particle includes an active material. The covering layer includes a first layer and a second layer. At least part of the first layer is interposed between the core particle and the second layer. The first layer includes a first solid electrolyte. The second layer includes a second solid electrolyte. The first solid electrolyte is a fluoride. The second solid electrolyte is a sulfide.

Abstract: Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.

Abstract: An active material, a solid electrolyte, and a solvent are hard-kneaded to prepare a first electrode material. A dispersion promotion component is added to the first electrode material to prepare a second electrode material. Slurry containing the second electrode material is prepared. An electrode is produced by applying the slurry to a surface of a base material. A composite body is formed by the solid electrolyte adhering to a surface of the active material. The dispersion promotion component promotes dispersion of the solid electrolyte in the solvent.

Abstract: Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.

Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

Abstract: A solid electrolyte of the present disclosure includes: a porous dielectric having a plurality of pores interconnected mutually; and an electrolyte including a metal salt and at least one selected from the group consisting of an ionic compound and a bipolar compound and at least partially filling an interior of the plurality of pores. Inner surfaces of the plurality of pores of the porous dielectric are at least partially modified by a functional group containing a halogen atom.

Abstract: An all-solid-state battery comprises a power generation element and a restraint member. The restraint member applies a pressure of 0.5 MPa or less to the power generation element. The power generation element includes a positive electrode layer, a solid electrolyte layer, and a negative electrode layer. The solid electrolyte layer is interposed between the positive electrode layer and the negative electrode layer. The positive electrode layer includes a composite particle. The composite particle includes a positive electrode active material particle and a covering layer. The covering layer covers at least part of a surface of the positive electrode active material particle. The covering layer includes a sulfide solid electrolyte.

Abstract: Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.

Abstract: A solid electrolyte includes lithium, phosphorus, sulfur, and halogen, in which, when the solid electrolyte is measured by TG-MS, a first peak derived from cyclic sulfur appears in a temperature range of 170° C. or higher and lower than 250° C., a second peak derived from the cyclic sulfur appears in a temperature range of 250° C. or higher and lower than 300° C., and a peak intensity P1 of the first peak is higher than a peak intensity P2 of the second peak.

Abstract: A negative electrode active material of the present disclosure includes: a graphite particle having a void inside; and a first solid electrolyte. The void has a void size of 1 nm or more and 300 nm or less. The first solid electrolyte is present in the void. The graphite particle has, for example, a plurality of voids inside. The graphite particle has an average void size, determined by a mercury intrusion method, of, for example, 1 nm or more and 300 nm or less.

Abstract: A solid electrolyte of the present disclosure includes: a porous dielectric having a plurality of pores interconnected; and an electrolyte including a metal salt and at least one selected from the group consisting of an ionic compound and a bipolar compound and at least partially filling an interior of the plurality of pores. The porous dielectric includes a polyether structure. The plurality of pores have an average pore diameter of 20 nm or more and 100 nm or less.

Abstract: A solid-state battery of the present disclosure includes: a negative electrode layer including a negative electrode active material; a positive electrode layer; a solid electrolyte layer positioned between the positive electrode layer and the negative electrode layer. The negative electrode active material includes: a graphite particle being an aggregate of a plurality of primary particles including graphite, the graphite particle having a void inside; and a solid electrolyte being present in the void. At least a portion of the void may be filled with the solid electrolyte. The void has a minimum diameter of, for example, 1 nm or more and 70 nm or less.

Abstract: A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.

Abstract: A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.

Abstract: A positive-electrode material according to the present disclosure includes a positive-electrode active material and a cover layer 111 containing a first solid electrolyte and covering at least partially the surface of the positive-electrode active material. The positive-electrode active material and the cover layer constitute a covered active material; the positive-electrode active material has a pore volume V?, the covered active material has a pore volume V?, the positive-electrode active material has a specific surface area Sa, the covered active material has a specific surface area Sp, and at least one selected from the group consisting of 0.20<V?/V?<0.88 and 0.81<S?/S?<0.97 is satisfied.

Abstract: A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.