Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: Technology for a non-volatile storage system and method of operating a non-volatile storage system that recycles current (e.g., Icc) to reduce the amount of current used during sense operations. The memory system applies voltages to memory cells that result in first currents flowing through a first set of NAND strings and second currents flowing through a second set of NAND strings. During the sense operation a first set of sense amplifiers sense selected memory cells on the first set of NAND strings and a second set of sense amplifiers sense selected memory cells on the second set of NAND strings. The memory system operates the first set of sense amplifiers and the set plurality of sense amplifiers to recycle the first currents for use as a current source for the second currents during the sense operation.

Abstract: An active material, a solid electrolyte, and a solvent are hard-kneaded to prepare a first electrode material. A dispersion promotion component is added to the first electrode material to prepare a second electrode material. Slurry containing the second electrode material is prepared. An electrode is produced by applying the slurry to a surface of a base material. A composite body is formed by the solid electrolyte adhering to a surface of the active material. The dispersion promotion component promotes dispersion of the solid electrolyte in the solvent.

Abstract: Technology for testing non-volatile memory. The memory system uses a single set of “n” common global interconnect (CGI) lines to test blocks of memory cells, with each block having “n” word lines. There is a set “n” word line switches associated with each block of memory cells, with each block having n word lines. Each CGI line connects to one word line switch in each set of word line switches. However, the mapping of the CGI lines to word line switches differs between the odd blocks and the even blocks. A single set of CGI lines to be used for tests involving adjacent blocks such as leakage current tests and stress tests. Moreover, this single set of CGI lines may also be used for normal memory operations such as read, write, and erase.

Abstract: A solid-state battery of the present disclosure includes: a negative electrode layer including a negative electrode active material; a positive electrode layer; a solid electrolyte layer positioned between the positive electrode layer and the negative electrode layer. The negative electrode active material includes: a graphite particle being an aggregate of a plurality of primary particles including graphite, the graphite particle having a void inside; and a solid electrolyte being present in the void. At least a portion of the void may be filled with the solid electrolyte. The void has a minimum diameter of, for example, 1 nm or more and 70 nm or less.

Abstract: The memory device that includes a planes with memory blocks that have memory cells arranged in word lines. The memory device also includes circuitry that is configured to receive a read command for a selected memory block of the plurality of planes. The circuitry is also configured to determine a count of planes of the plurality of planes that have memory blocks undergoing a block activation process, which includes ramping the plurality of word lines to a pass voltage. In response to the count being below or equal to a predetermined threshold, the circuitry begins the block activation process for the selected memory block. In response to the count being above the predetermined threshold, the circuitry delays the block activation process for the selected memory block until the number of planes that have memory blocks undergoing the block activation process is below the predetermined threshold.

Abstract: A positive electrode material according to the present disclosure includes: a positive electrode active material; a coating material including a first conductive material and a first solid electrolyte, the coating material coating at least a portion of a surface of the positive electrode active material; a second conductive material that is a fibrous carbon material; and a second solid electrolyte. The first solid electrolyte includes Li, Ti, M, and F, and the M is at least one selected from the group consisting of Ca, Mg, Al, Y, and Zr. The second conductive material has an average fiber diameter of 0.4 nm or more and 50 nm or less.

Abstract: A method for producing electrode composite powder according to the present disclosure includes: (a) kneading active material particles and a sulfide solid electrolyte while adding a solvent; and (b) after step (a), kneading the active material particles and the sulfide solid electrolyte without adding a solvent, so as to at least partially deform the sulfide solid electrolyte and coat at least part of a surface of the active material particles with the sulfide solid electrolyte. The kneading speed in step (a) is lower than the kneading speed in step (b). The electrode composite powder includes the active material particles and the sulfide solid electrolyte.

Abstract: Provided is a composite active material that is capable of more suppressing deterioration of an active material caused by the moisture of the composite active material than a conventional composite active material by increasing a permissible water content of a layer of the composite active material. The composite active material that is used for solid-state batteries includes: an active material; a first coat layer that contains a fluoride-containing first solid electrolyte, the first coat layer coating at least part of a surface of the active material; and a second coat layer that contains a sulfide-containing second solid electrolyte, and a solvent, the second coat layer coating at least part of the first coat layer, wherein a water content of the composite active material at 200° C. measures at most 823 ppm on a Karl Fischer titrator.

Abstract: A memory device includes a plurality of memory blocks including respective word lines; and a word line driver circuit including word line driver transistors. In one embodiment, the word line driver transistors are located in laterally offset rows. In another embodiment, at least one of a spacing between laterally adjacent word line driver transistors or a length of their source or drain region differs dependent on whether the transistors are connected to words lines in the same memory block or in different memory blocks.

Abstract: A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.

Abstract: Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.

Abstract: A solid electrolyte composition of the present disclosure including a solvent, an active material, and a solid electrolyte, is powdery or clayey, in which the active material and the solid electrolyte form a composite. A solid content ratio of the solid electrolyte composition is, for example, 72 mass % or more and 88 mass % or less. An electrode slurry is obtainable by adding a solvent to the solid electrolyte composition. An electrode and a battery can be produced using the electrode slurry.

Abstract: An apparatus is provided that includes a three dimensional array of non-volatile memory cells, and a control circuit configured to control the three dimensional memory array. The control circuit includes a first number of sense amplifier tiers, each having sense amplifiers arranged along a first axis, a second number of bit line switch regions, each having bit line switches, each bit line switch coupled to a corresponding one of the sense amplifiers, the second number greater than the first number, and a plurality of cross bit lines routed along an axis parallel to the first axis and arranged along a second axis perpendicular to the first axis, each cross bit line coupled to a corresponding one of the bit line switches. Each bit line switch is configured to selectively couple a corresponding one of the cross bit lines to a corresponding one of the sense amplifiers.

Abstract: A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

Abstract: An electrode material has a solid concentration of 72% or more. It includes a composite particle, a sulfide solid electrolyte, and a solvent. The composite particle includes an active material and a fluoride solid electrolyte. The fluoride solid electrolyte covers at least part of a surface of the active material. The sulfide solid electrolyte is adhered to the composite particle.

Abstract: A negative electrode active material according to one aspect of the present disclosure includes: a porous silicon particle; a solid electrolyte; and a carbon material, wherein the porous silicon particle has a plurality of pores, the solid electrolyte and the carbon material cover at least a part of an inner surface of each of the pores, and the solid electrolyte is in contact with the carbon material inside the pores.

Abstract: There is provided a positive electrode material that can be used to manufacture a solid-state battery whose initial resistance is kept low and at which it is difficult for resistance to increase even if charging/discharging are repeated. The positive electrode material of the present disclosure contains a positive electrode active material complex and a sulfide solid electrolyte. The positive electrode active material complex contains: a positive electrode active material, a conductive additive covering at least a portion of a surface of the positive electrode active material, and a solid electrolyte covering at least a portion of the conductive additive. The solid electrolyte contains Li, Ti, X and F. The X is at least one selected from the group consisting of Ca, Mg, Al, Y and Zr.