Patents by Inventor Hiroki Yabe

Hiroki Yabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220300162
    Abstract: A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroki Yabe, Masahito Takehara
  • Patent number: 11433677
    Abstract: A liquid filling method of filling a liquid storage device including a first tank that stores a liquid to be supplied to an ejection head ejecting the liquid and a second tank that stores the liquid to be supplied to the first tank through a connection port provided in the first tank with the liquid, the method including: injecting the liquid from a liquid storage container into the first tank through a first liquid introduction port provided in the first tank, in a state where a second liquid introduction port provided in the second tank is closed.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsushi Omura, Hiroki Tajima, Keiichiro Tsukuda, Kenji Yabe, Yuji Tamaru, Naoko Shimizu, Sayaka Seki, Yosuke Takagi, Shimpei Yoshikawa, Ryo Sato, Kyosuke Toda
  • Patent number: 11405039
    Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first NMOS transistor and a first PMOS transistor in series with a first input node and a negative amplified voltage, and the second leg includes a second NMOS transistor and a second PMOS transistor in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 2, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Publication number: 20220208270
    Abstract: A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Keiji Nose, Hiroki Yabe, Masahiro Kano, Yuki Fujita
  • Patent number: 11348649
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Patent number: 11336283
    Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: May 17, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Patent number: 11250920
    Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 15, 2022
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Publication number: 20210407604
    Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Publication number: 20210359325
    Abstract: A redox flow battery includes a negative electrode; a positive electrode; a first liquid which contains a first nonaqueous solvent, a first redox species, and metal ions and which is in contact with the negative electrode; a second liquid which contains a second nonaqueous solvent and which is in contact with the positive electrode; and a metal ion-conducting membrane disposed between the first liquid and the second liquid. The metal ion-conducting membrane contains a plurality of inorganic particles and a binder which contains an organic polymer and which binds the inorganic particles together.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Inventors: HONAMI SAKO, MASAHISA FUJIMOTO, HIROKI YABE, SHUJI ITO
  • Patent number: 11177277
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Patent number: 11158384
    Abstract: An apparatus is provided that includes a plurality of NAND strings having a common set of word lines. Each NAND string includes data memory cells for data storage and dummy memory cells connected in series with the data memory cells. A first group of NAND strings includes dummy memory cells with a first pattern of threshold voltages and a second group of NAND strings includes dummy memory cells with a second pattern of threshold voltages for separate isolation of data memory cells of the first and second groups of NAND strings from corresponding bit lines.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 26, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Publication number: 20210319833
    Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 14, 2021
    Applicant: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Patent number: 11087800
    Abstract: A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 10, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Patent number: 11081192
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 11081167
    Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 3, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi
  • Publication number: 20210142858
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 11004518
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
  • Publication number: 20210134828
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Publication number: 20210134375
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa