Abstract: A semiconductor device includes a plurality of memory blocks and a bit-line-bias block. A source-drain erase bias voltage is applied between a source line and a bit lines through the bit-line-bias block during an erase operation.

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

Abstract: An electrode material has a solid concentration of 72% or more. It includes a composite particle, a sulfide solid electrolyte, and a solvent. The composite particle includes an active material and a fluoride solid electrolyte. The fluoride solid electrolyte covers at least part of a surface of the active material. The sulfide solid electrolyte is adhered to the composite particle.

Abstract: A negative electrode active material according to one aspect of the present disclosure includes: a porous silicon particle; a solid electrolyte; and a carbon material, wherein the porous silicon particle has a plurality of pores, the solid electrolyte and the carbon material cover at least a part of an inner surface of each of the pores, and the solid electrolyte is in contact with the carbon material inside the pores.

Abstract: There is provided a positive electrode material that can be used to manufacture a solid-state battery whose initial resistance is kept low and at which it is difficult for resistance to increase even if charging/discharging are repeated. The positive electrode material of the present disclosure contains a positive electrode active material complex and a sulfide solid electrolyte. The positive electrode active material complex contains: a positive electrode active material, a conductive additive covering at least a portion of a surface of the positive electrode active material, and a solid electrolyte covering at least a portion of the conductive additive. The solid electrolyte contains Li, Ti, X and F. The X is at least one selected from the group consisting of Ca, Mg, Al, Y and Zr.

Abstract: A negative electrode active material according to one aspect of the present disclosure includes: a porous silicon particle; and a solid electrolyte, wherein the porous silicon particle has a plurality of pores, the solid electrolyte has a shape of a thin film that covers at least a part of an inner surface of each of the pores, and the thin film has an average thickness of less than 30 nm.

Abstract: A battery includes: a positive electrode; a negative electrode; and a solid electrolyte layer disposed between the positive electrode and the negative electrode, in which the negative electrode includes a first negative electrode layer and a second negative electrode layer disposed between the first negative electrode layer and the solid electrolyte layer, the first negative electrode layer and the second negative electrode layer contain silicon, and the mole ratio of lithium to silicon in the second negative electrode layer is greater than the mole ratio of lithium to silicon in the first negative electrode layer.

Abstract: A negative electrode material according to the present disclosure includes a plurality of composite particles including an active material containing silicon, a first solid electrolyte, and a first conductive material and a second solid electrolyte, wherein the second solid electrolyte is present between the composite particle and the composite particle.

Abstract: A negative electrode active material according to one aspect of the present disclosure includes: a porous silicon particle; and a carbon material, wherein the porous silicon particle has a plurality of pores, the carbon material covers at least a part of an inner surface of each of the pores, and a ratio of a specific surface area of the negative electrode active material to a specific surface area of the porous silicon particle is 40% or more and 99% or less.

Abstract: A negative electrode active material according to one aspect of the present disclosure includes a plurality of porous silicon particles; and a plurality of fibrous carbon particles, wherein the porous silicon particle has a plurality of pores, each of the plurality of fibrous carbon particles is bonded to an outer surface of the porous silicon particle, and a ratio of an average fiber diameter of the plurality of fibrous carbon particles to an average particle diameter of the plurality of porous silicon particles is 1/10 or less.

Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.

Abstract: An electrode material has a solid concentration of 72% or more. It includes a composite particle, a sulfide solid electrolyte, and a solvent. The composite particle includes an active material and a fluoride solid electrolyte. The fluoride solid electrolyte covers at least part of a surface of the active material. The sulfide solid electrolyte is adhered to the composite particle.

Abstract: An electrode includes an active material layer. The active material layer includes a composite particle and an imidazoline-based compound. The composite particle includes a core particle and a covering layer. The covering layer covers at least part of a surface of the core particle. The core particle includes an active material. The covering layer includes a first layer and a second layer. At least part of the first layer is interposed between the core particle and the second layer. The first layer includes a first solid electrolyte. The second layer includes a second solid electrolyte. The first solid electrolyte is a fluoride. The second solid electrolyte is a sulfide.

Abstract: An electrode material comprises a composite particle. The composite particle includes a core particle and a covering layer. The covering layer covers at least part of a surface of the core particle. The core particle includes an active material. The covering layer includes a first layer and a second layer. At least part of the first layer is interposed between the core particle and the second layer. The first layer includes a first solid electrolyte. The second layer includes a second solid electrolyte. The first solid electrolyte is a fluoride. The second solid electrolyte is a sulfide.

Abstract: Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.

Abstract: An active material, a solid electrolyte, and a solvent are hard-kneaded to prepare a first electrode material. A dispersion promotion component is added to the first electrode material to prepare a second electrode material. Slurry containing the second electrode material is prepared. An electrode is produced by applying the slurry to a surface of a base material. A composite body is formed by the solid electrolyte adhering to a surface of the active material. The dispersion promotion component promotes dispersion of the solid electrolyte in the solvent.

Abstract: Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.

Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.