Patents by Inventor Hiroshi Ashihara
Hiroshi Ashihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9812355Abstract: A method of manufacturing a semiconductor device includes providing a substrate having an insulating film and a plurality of conductive films on a surface; reducing the substrate by supplying a first reducing gas to the substrate so that at least one of a plurality of process conditions of the first reducing gas is controlled so that a product of a plurality of process conditions becomes a predetermined value, wherein the process conditions of the first reducing gas include a partial pressure of the first reducing gas in a region where the substrate exists and a time taken to supply the first reducing gas to the substrate corresponding to a temperature of the first reducing gas; and selectively forming a metal film on the plurality of the reduced conductive films by supplying a second reducing gas and a metal-containing gas to the substrate.Type: GrantFiled: September 29, 2016Date of Patent: November 7, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kimihiko Nakatani, Hiroshi Ashihara
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Publication number: 20170287731Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.Type: ApplicationFiled: March 16, 2017Publication date: October 5, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Tsuyoshi TAKEDA, Hiroshi ASHIHARA, Naofumi OHASHI, Toshiyuki KIKUCHI
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Patent number: 9728400Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber; exhausting the precursor gas in the process chamber through an exhaust system; confining a reaction gas, which differs in chemical structure from the precursor gas, in the process chamber by supplying the reaction gas to the substrate in the process chamber while the exhaust system is closed; and exhausting the reaction gas in the process chamber through the exhaust system while the exhaust system is opened.Type: GrantFiled: January 29, 2016Date of Patent: August 8, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takeo Hanashima, Hiroshi Ashihara
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Patent number: 9728409Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second metal nitride film on a substrate by alternately performing steps (a) and (b) a plurality of times, wherein the step (a) includes alternately supplying: a first metal source containing a first halogen element and a metal element; and a nitrogen-containing source to the substrate a plurality of times to form the first metal nitride film, and the step (b) includes alternately supplying: a second metal source containing a second halogen element different from the first halogen element and the metal element; and the nitrogen-containing source to the substrate a plurality of times to form the second metal nitride film.Type: GrantFiled: September 26, 2016Date of Patent: August 8, 2017Assignee: Hitachi Kokusai Electric Inc.Inventors: Kazuhiro Harada, Kimihiko Nakatani, Hiroshi Ashihara
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Publication number: 20170198391Abstract: A technique for performing high-temperature substrate processing includes a plurality of chambers where substrates are processed, wherein the chambers are disposed adjacent to one another; a gas supply unit configured to alternately supply first and second gasses to each of the chambers; a first exhaust pipe installed in each of the chambers and configured to exhaust the first and second gasses; a first heater installed at the first exhaust pipe and configured to heat the first exhaust pipe to a temperature higher than a temperature whereat a source of the first gas is vaporized under vapor pressure; an electronic box installed at each of the chambers, wherein the electronic box is disposed adjacent to a gas box accommodating a portion of the first exhaust pipe; and a thermal reduction structure surrounding the first exhaust pipe and configured to reduce heat from the first heater being conducted to the electronic box.Type: ApplicationFiled: March 18, 2016Publication date: July 13, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: Hiroshi ASHIHARA
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Patent number: 9698050Abstract: A method of manufacturing a semiconductor device includes loading, into a process chamber, a substrate including a first wiring layer having a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wiring insulating film insulating between the plurality of copper-containing films, and a void formed between the plurality of copper-containing films, and a first diffusion barrier film formed on a portion of an upper surface of the copper-containing films to suppress diffusion of a component of the copper-containing films, and forming a second diffusion barrier film configured to suppress diffusion of a component of the copper-containing films on a surface of another portion, on which the first diffusion barrier film is not formed, in the copper-containing films.Type: GrantFiled: July 29, 2016Date of Patent: July 4, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Hiroshi Ashihara, Naofumi Ohashi, Tsuyoshi Takeda, Toshiyuki Kikuchi
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Patent number: 9673043Abstract: There is provided a technique including: (a) forming a thin film containing a predetermined element, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element, carbon and a halogen element having a chemical bond between the predetermined element and carbon to the substrate; (a-2) supplying an oxidizing gas to the substrate; and (a-3) supplying a catalytic gas to the substrate; (b) removing a first impurity from the thin film by thermally processing the thin film at a first temperature higher than a temperature of the substrate in (a); and (c) removing a second impurity different from the first impurity from the thin film by thermally processing the thin film at a second temperature equal to or higher than the first temperature after performing (b).Type: GrantFiled: March 30, 2016Date of Patent: June 6, 2017Assignee: Hitachi Kokusai Electric Inc.Inventors: Takaaki Noda, Shingo Nohara, Satoshi Shimamoto, Hiroshi Ashihara, Takeo Hanashima, Yoshiro Hirose, Tsukasa Kamakura
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Patent number: 9659767Abstract: Generation of adhered materials in a space over a gas guide of a shower head is inhibited. A substrate processing apparatus includes a process chamber; a buffer chamber including a dispersion unit; a process gas supply hole installed in a ceiling portion of the buffer chamber; an inert gas supply hole installed in the ceiling portion; a gas guide disposed in a gap between the dispersion unit and the ceiling portion, the gas guide including a base end portion disposed at a side of the process gas supply hole, a leading end portion disposed closer to the inert gas supply hole than to the process gas supply hole, and a plate portion connecting the base end portion and the leading end portion; a process chamber exhaust unit; and a control unit.Type: GrantFiled: September 29, 2014Date of Patent: May 23, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Hidehiro Yanai, Hiroshi Ashihara, Atsushi Sano, Tadashi Takasaki
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Publication number: 20170092490Abstract: Provided is a technique for forming a film having a desired stress on a substrate. A method of manufacturing a semiconductor device includes: forming a film having a predetermined stress on a substrate by controlling a ratio of a thickness of a first film having compressive stress to a thickness of a second film having tensile stress by performing: (a) supplying an organic source gas containing a first element and a reactive gas containing a second element to the substrate to form the first film containing the first element and the second element; and (b) supplying an inorganic source gas containing the first element and the reactive gas to the substrate to form the second film containing the first element and the second element.Type: ApplicationFiled: September 26, 2016Publication date: March 30, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Hirohisa YAMAZAKI, Noriyuki ISOBE, Hiroshi ASHIHARA
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Publication number: 20170067157Abstract: A substrate processing apparatus includes: a process container where a substrate is processed; a process gas supply unit configured to supply a process gas into the process container; a substrate placing table installed in the process container; a shaft penetrating a hole at a bottom portion of the process container and coupled to the substrate placing table; a bellows surrounding the shaft and disposed outside of the process container wherein an inner space thereof is in communication with a space of the process container; an inert gas supply system configured to supply an inert gas into the inner space of the bellows disposed outside of the process container; and a component falling prevention unit including at least a first structure disposed along a first portion of the hole at the bottom of the process container and a second structure disposed along a second portion of the hole adjacent to the first structure.Type: ApplicationFiled: September 8, 2016Publication date: March 9, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Hiroshi ASHIHARA, Motoshi SAWADA
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Patent number: 9587313Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a plurality of substrates and to be supplied with a gas generated by vaporizing or turning into mist a solution containing a reactant in a solvent; a lid configured to close the reaction tube; a first heater configured to heat the plurality of substrates; a thermal conductor placed on the lid on an upper surface thereof; a second heater placed outside the reaction tube around a side thereof, the second heater being configured to heat the gas flowing near the lid; and a heating element placed on the lid on a lower surface thereof, the heating element configured to heat the lid.Type: GrantFiled: January 26, 2015Date of Patent: March 7, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Yuichi Wada, Hiroshi Ashihara, Hideto Tateno, Harunobu Sakuma
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Patent number: 9558937Abstract: A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b).Type: GrantFiled: October 19, 2015Date of Patent: January 31, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara, Ryuji Yamamoto
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Publication number: 20170011926Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second metal nitride film on a substrate by alternately performing steps (a) and (b) a plurality of times, wherein the step (a) includes alternately supplying: a first metal source containing a first halogen element and a metal element; and a nitrogen-containing source to the substrate a plurality of times to form the first metal nitride film, and the step (b) includes alternately supplying: a second metal source containing a second halogen element different from the first halogen element and the metal element; and the nitrogen-containing source to the substrate a plurality of times to form the second metal nitride film.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kazuhiro HARADA, Kimihiko NAKATANI, Hiroshi ASHIHARA
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Publication number: 20170004961Abstract: An oxide film is formed on a substrate by performing a cycle a predetermined number of times. The cycle includes: continuously performing supplying in advance an oxidant to a substrate in a process chamber and simultaneously supplying the oxidant and a precursor to the substrate in the process chamber, without having to purge an interior of the process chamber between the act of supplying in advance the oxidant and the act of simultaneously supplying the oxidant and the precursor; stopping the supply of the oxidant and the precursor to the substrate in the process chamber and purging the interior of the process chamber; and supplying the oxidant to the substrate in the purged process chamber.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takuro USHIDA, Tsukasa KAMAKURA, Hiroshi ASHIHARA, Kimihiko NAKATANI
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Patent number: 9536734Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber; exhausting the precursor gas in the process chamber through an exhaust system; confining a reaction gas, which differs in chemical structure from the precursor gas, in the process chamber by supplying the reaction gas to the substrate in the process chamber while the exhaust system is closed; and exhausting the reaction gas in the process chamber through the exhaust system while the exhaust system is opened.Type: GrantFiled: February 11, 2015Date of Patent: January 3, 2017Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Takeo Hanashima, Hiroshi Ashihara
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Patent number: 9508546Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes (a) loading a substrate into a process chamber; (b) processing the substrate by supplying a process gas into the process chamber via a shower head disposed above the process chamber and including a buffer chamber; (c) unloading the substrate from the process chamber; and (d) cleaning the buffer chamber and the process chamber after performing the step (c), wherein the step (d) comprises: (d-1) cleaning the buffer chamber by a plasma generation from a cleaning gas in the buffer chamber by a plasma generation unit including a plasma generation region switching unit; and (d-2) cleaning the process chamber by switching the plasma generation from the cleaning gas in the buffer chamber to a plasma generation from the cleaning gas in the process chamber by the plasma generation region switching unit.Type: GrantFiled: December 11, 2014Date of Patent: November 29, 2016Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kazuyuki Toyoda, Tadashi Takasaki, Hiroshi Ashihara, Atsushi Sano, Naonori Akae, Hidehiro Yanai
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Publication number: 20160293421Abstract: A method of manufacturing a semiconductor device includes forming a metal-containing film including a first element that is a metal element and a second element by performing a predetermined number of times in a time-division manner a cycle of supplying an organic metal source gas containing the first element to a substrate, supplying a halogen-based metal source gas containing the first element to the substrate and supplying a reaction gas, which contains the second element and which reacts with the first element, to the substrate, wherein a value of film stress of the metal-containing film is controlled by controlling at least one value of a supply flow rate and a supply time of the organic metal source gas in the act of supplying an organic metal source gas.Type: ApplicationFiled: March 21, 2016Publication date: October 6, 2016Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kazuhiro HARADA, Arito OGAWA, Motomu DEGAI, Masahito KITAMURA, Hiroshi ASHIHARA
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Patent number: 9418855Abstract: A halogen element-containing metal material and a nitrogen-containing material are alternately supplied to a process chamber with a flow rate of an inert gas supplied to the process chamber together with the nitrogen-containing material during the supplying of the nitrogen-containing material to the process chamber being more increased than a flow rate of the inert gas supplied to the process chamber together with the metal material during the supplying of the metal material to the process chamber.Type: GrantFiled: March 24, 2015Date of Patent: August 16, 2016Assignee: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara
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Publication number: 20160233085Abstract: A film containing a prescribed element and carbon is formed on a substrate, by performing a cycle a prescribed number of times, the cycle including: supplying an organic-based source containing a prescribed element and a pseudo catalyst including at least one selected from the group including a halogen compound and a boron compound, into a process chamber in which the substrate is housed, and confining the organic-based source and the pseudo catalyst in the process chamber; maintaining a state in which the organic-based source and the pseudo catalyst are confined in the process chamber; and exhausting an inside of the process chamber.Type: ApplicationFiled: September 27, 2013Publication date: August 11, 2016Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Daigo YAMAGUCHI, Tsukasa KAMAKURA, Hiroshi ASHIHARA, Tsuyoshi TAKEDA, Taketoshi SATO
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Publication number: 20160218012Abstract: A fine pattern-forming method includes: a core pattern-forming step of forming a core pattern of a predetermined line width at a substrate surface side; a sidewall-forming step of forming a sidewall on the core pattern formed in the core pattern-forming step; and a core pattern removing step of removing the core pattern in a state where the sidewall is left, by using an etching gas after the sidewall-forming step, and is configured such that, in the core pattern removing step, a film deposited at a substrate back side in the core pattern-forming step is removed in parallel to the removal of the core pattern.Type: ApplicationFiled: September 29, 2014Publication date: July 28, 2016Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Satoshi SHIMAMOTO, Toshiyuki KIKUCHI, Jiro YUGAMI, Yoshiro HIROSE, Yuichi WADA, Kenji KANAYAMA, Hiroshi ASHIHARA, Kenji KAMEDA