Patents by Inventor Hiroshi Ashihara

Hiroshi Ashihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082797
    Abstract: A substrate processing apparatus capable of increasing the life span of a lamp for heating a substrate is provided. The substrate processing apparatus includes: a light receiving chamber for processing a substrate; a substrate support unit inside the light receiving chamber; a lamp including an electrical wire, and a seal accommodating the electrical wire to hermetically seal the lamp with a gas therein, the lamp irradiating the substrate with a light; a lamp receiving unit outside the light receiving chamber to accommodate the lamp therein, the lamp receiving unit including a lamp connector connected to the lamp to supply an electric current through the electrical wire, a heat absorption member including a material having a thermal conductivity higher than that of the seal, and a base member fixing the heat absorption member; and an external electrical wire connected to the lamp connector to supply current to the lamp connector.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 14, 2015
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yukinori Aburatani, Toshiya Shimada, Kenji Shinozaki, Tomihiro Amano, Hiroshi Ashihara, Hidehiro Yanai, Masahiro Miyake, Shin Hiyama
  • Publication number: 20150187567
    Abstract: A substrate processing apparatus processes a substrate by supplying a gas into a processing space. The apparatus includes a buffer space wherein the gas is dispersed, the buffer space disposed at an upstream side of the processing space; a transfer space where the substrate passes when transferred to the processing space; a first, a second and a third exhaust pipe connected to the transfer space, the buffer space and the processing space, respectively; a fourth exhaust pipe connected to downstream sides of the first exhaust pipe, the second exhaust pipe and the third exhaust pipe; a first vacuum pump disposed at the first exhaust pipe; a second vacuum pump disposed at the fourth exhaust pipe; a first valve disposed at the first exhaust pipe at a downstream side of the first vacuum pump; and a second and a third valve disposed at the second and the third exhaust pipe, respectively.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 2, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hiroshi ASHIHARA, Arito OGAWA
  • Patent number: 9059089
    Abstract: A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 16, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Harada, Arito Ogawa, Hiroshi Ashihara
  • Publication number: 20150140835
    Abstract: A substrate processing apparatus is disclosed. The substrate processing apparatus includes a process chamber configured to accommodate a substrate; a gas supply unit configured to supply a process gas into the process chamber; a lid member configured to block an end portion opening of the process chamber; an end portion heating unit installed around a side wall of an end portion of the process chamber; and a thermal conductor installed on a surface of the lid member in an inner side of the process chamber, and configured to be heated by the end portion heating unit.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hideto TATENO, Yuichi WADA, Hiroshi ASHIHARA, Keishin YAMAZAKI, Takurou USHIDA, Iwao NAKAMURA, Manabu IZUMI
  • Publication number: 20150132972
    Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a plurality of substrates and to be supplied with a gas generated by vaporizing or turning into mist a solution containing a reactant in a solvent; a lid configured to close the reaction tube; a first heater configured to heat the plurality of substrates; a thermal conductor placed on the lid on an upper surface thereof; a second heater placed outside the reaction tube around a side thereof, the second heater being configured to heat the gas flowing near the lid; and a heating element placed on the lid on a lower surface thereof, the heating element configured to heat the lid.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 14, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yuichi WADA, Hiroshi ASHIHARA, Hideto TATENO, Harunobu SAKUMA
  • Publication number: 20150093911
    Abstract: A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b).
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Kimihiko NAKATANI, Kazuhiro HARADA, Hiroshi ASHIHARA, Ryuji YAMAMOTO
  • Patent number: 8986450
    Abstract: Generation of adhered materials in a space over a gas guide of a shower head is inhibited. A substrate processing apparatus includes a process chamber; a buffer chamber including a dispersion unit; a process gas supply hole installed in a ceiling portion of the buffer chamber; an inert gas supply hole installed in the ceiling portion; a gas guide disposed in a gap between the dispersion unit and the ceiling portion, the gas guide including a base end portion disposed at a side of the process gas supply hole, a leading end portion disposed closer to the inert gas supply hole than to the process gas supply hole, and a plate portion connecting the base end portion and the leading end portion; a process chamber exhaust unit; and a control unit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 24, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hidehiro Yanai, Hiroshi Ashihara, Atsushi Sano, Tadashi Takasaki
  • Patent number: 8925562
    Abstract: A substrate processing apparatus includes a first gas supply system provided with a source gas supply control unit; a second gas supply system provided with a reactive gas supply control unit; a third gas supply system provided with a cleaning gas supply control unit; a shower head unit including a buffer chamber connected to the gas supply systems and a dispersion plate installed at a downstream side of the buffer chamber; a substrate support installed at a downstream side of the dispersion plate and electrically grounded; a process chamber accommodating the substrate support; a plasma generation unit including a power supply and a switch configured to switch plasma generation between the buffer chamber and the process chamber; and a control unit configured to control the source gas supply control unit, the reactive gas supply control unit and the plasma generation unit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 6, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuyuki Toyoda, Tadashi Takasaki, Hiroshi Ashihara, Atsushi Sano, Naonori Akae, Hidehiro Yanai
  • Publication number: 20140302687
    Abstract: A substrate processing apparatus includes: a reaction chamber configured to process a substrate; a vaporizer including a vaporization container into which a processing liquid including hydrogen peroxide or hydrogen peroxide and water is supplied, a processing liquid supply unit configured to supply the processing liquid to the vaporization container, and a heating unit configured to heat the vaporization container; a gas supply unit configured to supply a processing gas generated by the vaporizer into the reaction chamber; an exhaust unit configured to exhaust an atmosphere in the reaction chamber; and a control unit configured to control the heating unit and the processing liquid supply unit such that the processing liquid supply unit supplies the processing liquid to the vaporization container while the heating unit heats the vaporization container.
    Type: Application
    Filed: June 20, 2014
    Publication date: October 9, 2014
    Inventors: Hiroshi ASHIHARA, Harunobu SAKUMA, Hideto TATENO, Yuichi WADA
  • Publication number: 20140287595
    Abstract: A thin film having excellent etching resistance and a low dielectric constant is described. A method of manufacturing a semiconductor device includes forming a thin film on a substrate, removing first impurities containing H2O and Cl from the thin film by heating the thin film at a first temperature higher than a temperature of the substrate in the forming of the thin film, and removing second impurities containing a hydrocarbon compound (CxHy-based impurities) from the thin film in which heat treatment is performed at the first temperature by heating the thin film at a second temperature equal to or higher than the first temperature.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Takaaki Noda, Takeo Hanashima, Yoshiro Hirose, Hiroshi Ashihara, Tsukasa Kamakura, Shingo Nohara
  • Publication number: 20140256160
    Abstract: An apparatus for manufacturing semiconductor devices is provided with a processing liquid supply part for supplying processing liquid into a processing chamber which houses a substrate, a heater part for heating the processing liquid in the processing chamber, and a substrate support part which is provided in the processing chamber and supports the substrate.
    Type: Application
    Filed: May 21, 2014
    Publication date: September 11, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Yuichi Wada, Harunobu Sakuma, Hiroshi Ashihara, Hideto Tateno
  • Publication number: 20140242790
    Abstract: A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 28, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuhiro HARADA, Arito OGAWA, Hiroshi ASHIHARA
  • Publication number: 20140235068
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes (a) loading a substrate having a silicon-containing film formed thereon into a process chamber; (b) supplying a gas into the process chamber from a gas supply unit until an inner pressure of the process chamber is equal to or greater than atmospheric pressure; and (c) supplying a process liquid from a process liquid supply unit to the substrate to oxidize the silicon-containing film.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Hiroshi ASHIHARA, Tomihiro AMANO, Shin HIYAMA, Harunobu SAKUMA, Yuichi WADA, Hideto TATENO
  • Publication number: 20130012035
    Abstract: A substrate processing apparatus capable of increasing the life span of a lamp for heating a substrate is provided. The substrate processing apparatus includes: a light receiving chamber for processing a substrate; a substrate support unit inside the light receiving chamber; a lamp including an electrical wire, and a seal accommodating the electrical wire to hermetically seal the lamp with a gas therein, the lamp irradiating the substrate with a light; a lamp receiving unit outside the light receiving chamber to accommodate the lamp therein, the lamp receiving unit including a lamp connector connected to the lamp to supply an electric current through the electrical wire, a heat absorption member including a material having a thermal conductivity higher than that of the seal, and a base member fixing the heat absorption member; and an external electrical wire connected to the lamp connector to supply current to the lamp connector.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 10, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinori Aburatani, Toshiya Shimada, Kenji Shinozaki, Tomihiro Amano, Hiroshi Ashihara, Hidehiro Yanai, Masahiro Miyake, Shin Hiyama
  • Patent number: 7981761
    Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: July 19, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Toshinori Imai, Tsuyoshi Fujiwara, Hiroshi Ashihara, Akira Ootaguro, Yoshihiro Kawasaki
  • Patent number: 7777346
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 17, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20100181647
    Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
    Type: Application
    Filed: March 30, 2010
    Publication date: July 22, 2010
    Inventors: Toshinori IMAI, Tsuyoshi Fujiwara, Hiroshi Ashihara, Akira Ootaguro, Yoshihiro Kawasaki
  • Patent number: 7569476
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20090115063
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 7, 2009
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20090111122
    Abstract: It is found that blood cytochrome c levels quantified for non-alcoholic steatohepatitis patients are higher than those for healthy persons, and that the quantified blood cytochrome c values correlated with fat deposition rates in hepatocytes. It is possible to test non-alcoholic steatohepatitis by quantifying cytochrome c in serum. A test method and a test kit for the test are provided.
    Type: Application
    Filed: April 6, 2007
    Publication date: April 30, 2009
    Applicants: Eisai R&D Management Co., Ltd., National University Corp. Kumamoto University
    Inventors: Yutaka Sasaki, Hiroshi Ashihara, Hiroyasu Nagahama, Muneo Aoyama