Patents by Inventor Hiroshi Horikoshi

Hiroshi Horikoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389705
    Abstract: A semiconductor device includes a first electrode which is provided in a first substrate and of which one surface is positioned on the same surface as a bonding surface between the first substrate and a second substrate, and a second electrode which is provided in the second substrate and of which one surface is positioned on the same surface as a bonding surface and bonded to one surface of the first electrode. Therefore, the semiconductor device includes at least one of a first capacitor which is provided in the first substrate and of which one electrode is electrically connected to a non-exposed surface of the first electrode and a second capacitor which is provided in the second substrate and of which one electrode is electrically connected to a non-exposed surface of the second electrode.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 12, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroshi Horikoshi
  • Patent number: 12389706
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
    Type: Grant
    Filed: May 20, 2024
    Date of Patent: August 12, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Patent number: 12349496
    Abstract: A semiconductor device includes a first electrode which is provided in a first substrate and of which one surface is positioned on the same surface as a bonding surface between the first substrate and a second substrate, and a second electrode which is provided in the second substrate and of which one surface is positioned on the same surface as a bonding surface and bonded to one surface of the first electrode. Therefore, the semiconductor device includes at least one of a first capacitor which is provided in the first substrate and of which one electrode is electrically connected to a non-exposed surface of the first electrode and a second capacitor which is provided in the second substrate and of which one electrode is electrically connected to a non-exposed surface of the second electrode.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 1, 2025
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroshi Horikoshi
  • Publication number: 20240304649
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi KAMESHIMA, Hideto HASHIGUCHI, Ikue MITSUHASHI, Hiroshi HORIKOSHI, Reijiroh SHOHJI, Minoru ISHIDA, Tadashi IIJIMA, Masaki HANEDA
  • Patent number: 12080745
    Abstract: A solid-state imaging device is provided that comprises a first substrate that includes a first multi-layered wiring layer stacked on a first semiconductor substrate, a second substrate that includes a second multi-layered wiring layer and an insulating layer stacked on a second semiconductor substrate, and a third substrate that includes a third multi-layered wiring layer stacked on a third semiconductor substrate. A first coupling structure electrically couples the first and second substrates to each other. A second coupling structure exists on bonding surfaces of the second and third substrates, and includes an electrode junction structure in which electrodes formed on respective bonding surfaces are in direct contact with each other. A first via penetrates the second semiconductor substrate and electrically couples a first electrode to a wiring in the second multi-layered wiring layer. A second via electrically couples the second electrode to another wiring in the third multi-layered wiring layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 3, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20240276114
    Abstract: The present technology relates to an imaging device and an electronic apparatus each capable of expanding a dynamic range without lowering a saturation charge quantity of a photodiode. There are provided a photoelectric conversion unit that converts light into charge, multiple storage portions that temporarily store charge, multiple transfer units that transfer charge to the storage portions, and a penetration trench that separates pixels. At least one of the multiple storage portions is a capacitive element. At least one of the multiple storage portions stores charge overflowing from the photoelectric conversion unit. For example, the present technology is applicable to an imaging device for capturing images.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuya UCHIDA, Shinji MIYAZAWA, Takeshi ISHIZAKI, Hirosato SHINTAKU, Hiroshi HORIKOSHI
  • Publication number: 20240274641
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Reijiroh SHOHJI, Masaki HANEDA, Hiroshi HORIKOSHI, Minoru ISHIDA, Takatoshi KAMESHIMA, Ikue MITSUHASHI, Hideto HASHIGUCHI, Tadashi IIJIMA
  • Patent number: 12057462
    Abstract: Provided is a solid-state imaging device that includes a first substrate which includes a first semiconductor substrate and a first multi-layered wiring layer that are stacked, a second substrate which includes a second semiconductor substrate and a second multi-layered wiring layer that are stacked, and a third substrate which includes a third semiconductor substrate and a third multi-layered wiring layer that are stacked. The solid-state imaging device further includes a first coupling structure for electrically coupling a circuit of the first substrate and a circuit of the second substrate to each other. The first coupling structure includes a via in which one through hole electrically couples a predetermined wiring line in the first multi-layered wiring layer, and a predetermined wiring line in the second multi-layered wiring layer or a predetermined wiring line in the third multi-layered wiring layer to each other.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 6, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
  • Patent number: 12027558
    Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Hiroshi Horikoshi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Masaki Haneda
  • Publication number: 20240213287
    Abstract: A solid-state imaging device and an electronic apparatus include: a first pixel provided on a side of a first surface serving as a side from which light enters of a first base, and a second pixel that is disposed in a first direction on the first surface to be adjacent to the first pixel; a first signal terminal that is provided in a region corresponding to a center portion of the first pixel on a side of a second surface of the first base and is coupled to the first pixel; a second signal terminal that is provided in a region corresponding to a center portion of the second pixel and is coupled to the second pixel; a first shield terminal that is provided in a region corresponding to a side of the second pixel of a peripheral portion of the first pixel on the side of the second surface; and a second shield terminal that is provided in a region corresponding to a side of the first pixel of a peripheral portion of the second pixel on the side of the second surface and is provided in a region displaced in a seco
    Type: Application
    Filed: January 12, 2022
    Publication date: June 27, 2024
    Inventor: HIROSHI HORIKOSHI
  • Publication number: 20240194718
    Abstract: To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Inventors: HIDETO HASHIGUCHI, REIJIROH SHOHJI, HIROSHI HORIKOSHI, IKUE MITSUHASHI, TADASHI IIJIMA, TAKATOSHI KAMESHIMA, MINORU ISHIDA, MASAKI HANEDA
  • Patent number: 11999824
    Abstract: The present application provides a composition for an optical material containing a compound (a) and/or a compound (b) and a compound (c) which are described below. The proportion of the compound (a) and/or the compound (b) is 0.001-30.0% by mass. The compound (a) is a compound represented by formula (1). The compound (b) is a compound represented by formula (2). The compound (c) is an episulfide compound.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: June 4, 2024
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yousuke Imagawa, Hiroshi Horikoshi
  • Patent number: 12002833
    Abstract: A solid-state imaging device including: a first substrate having a pixel unit, and a first semiconductor substrate and a first wiring layer; a second substrate with a circuit, and a second semiconductor substrate and a second wiring layer; and a third substrate with a circuit, and a third semiconductor substrate and a third wiring layer. The first and second substrates are bonded together such that the first wiring layer and the second semiconductor substrate are opposed to each other. The device includes a first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate. The first coupling structure includes a via in which electrically-conductive materials are embedded in a first through hole that exposes a wiring line in the first wiring layer and in a second through hole that exposes a wiring line in the second wiring layer or a film-formed structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Patent number: 11955500
    Abstract: There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Reijiroh Shohji, Masaki Haneda, Hiroshi Horikoshi, Minoru Ishida, Takatoshi Kameshima, Ikue Mitsuhashi, Hideto Hashiguchi, Tadashi Iijima
  • Patent number: 11948961
    Abstract: A solid-state imaging device including a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked, a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked, and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideto Hashiguchi, Reijiroh Shohji, Hiroshi Horikoshi, Ikue Mitsuhashi, Tadashi Iijima, Takatoshi Kameshima, Minoru Ishida, Masaki Haneda
  • Patent number: 11945791
    Abstract: The present invention makes it possible to provide a compound represented by formula (1) and a composition for an optical material containing this compound. (Where m+n=4, m represents an integer of from 0 to 3, and n represents an integer of from 1 to 4.) In addition, the present invention makes it possible to provide a method for producing an optical material, the method including a step for adding 0.0001-10 parts by mass of a polymerization catalyst per 100 parts by mass of the composition for an optical material, polymerizing, and curing.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 2, 2024
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Kouhei Takemura, Hiroshi Horikoshi
  • Patent number: 11919877
    Abstract: The present invention enables provision of a production method for 1,2,3,5,6-pentathiepane, the method comprising, in the following order, step A for reacting a trithiocarbonate, sulfur, and a methane dihalide together using a phase-transfer catalyst in a multilayer system having a water layer and an organic layer, step B for separating the water layer from the organic layer, and step C for stopping the reaction using an acid.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 5, 2024
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Hiroyuki Tanagi, Kouhei Takemura, Hiroshi Horikoshi
  • Publication number: 20240006448
    Abstract: Provided is an imaging device including: a first semiconductor substrate provided with a photoelectric conversion element, a second semiconductor substrate stacked on the first semiconductor substrate with an interlayer insulating film interposed therebetween and provided with a pixel circuit that reads out charges generated in the photoelectric conversion element as a pixel signal, and a via that penetrates the interlayer insulating film and electrically connects a first surface of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface of the second semiconductor substrate facing the first surface.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 4, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeya MOCHIZUKI, Keiichi NAKAZAWA, Shinichi YOSHIDA, Kenya NISHIO, Nobutoshi FUJII, Suguru SAITO, Masaki OKAMOTO, Ryosuke KAMATANI, Yuichi YAMAMOTO, Kazutaka IZUKASHI, Yuki MIYANAMI, Hirotaka YOSHIOKA, Hiroshi HORIKOSHI, Takuya KUROTORI, Shunsuke FURUSE, Takayoshi HONDA
  • Patent number: 11858920
    Abstract: Provided is a composition for optical materials that gives optical materials which can have at least one improved property selected from among satisfactory mold releasability after polymerization and curing, unsusceptibility to separation from the mold during polymerization and curing, transparency, and low-level striae. The present invention further provides a compound represented by formula (1). The composition for optical materials comprises the compound represented by formula (1) and a compound represented by formula (2). (In formula (1), X1 and X2 represent O or S, provided that both X1 and X2 are O or that X1 is O and X2 is S.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 2, 2024
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Kouhei Takemura, Yousuke Imagawa, Hiroshi Horikoshi
  • Patent number: 11804507
    Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 31, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ikue Mitsuhashi, Reijiroh Shohji, Minoru Ishida, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Hiroshi Horikoshi, Masaki Haneda