Patents by Inventor Hiroshi Ishihara
Hiroshi Ishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6131967Abstract: A door lock assembly having a reduced size. The door lock assembly comprises: a closer mechanism for bringing a vehicle door from a partially closed state to a completely closed state; a locking/unlocking mechanism for bringing the vehicle door in the completely closed state to a locked state and an unlocked state; and a drive mechanism including a single motor acting as a drive source for actuating the closer mechanism and the locking/unlocking mechanism.Type: GrantFiled: February 4, 1999Date of Patent: October 17, 2000Assignee: Aisin Seiki Kabushiki KaishaInventors: Ichiro Kondo, Hiroshi Ishihara, Toshitsugu Oda
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Patent number: 6057431Abstract: The present invention provides a compound of general formula (I): ##STR1## wherein X represents group (II) or (III): ##STR2## wherein Y represents a leaving group and Z represents an oligonucleotide. The compound can specifically transfer oligonucleotides to cells which specifically recognize a specified saccharide construction. Accordingly, the compound can be used as an antiviral agent or an antitumor agent.Type: GrantFiled: December 22, 1997Date of Patent: May 2, 2000Assignee: Drug Delivery System Institute, Ltd.Inventors: Hiroshi Ishihara, Takayuki Kawaguchi, Masahiro Ikeda, Kazutaka Nakamoto, Atsushi Sasaki
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Patent number: 5981366Abstract: A method for forming a non-volatile memory having a floating gate electrode arranged therein. The floating gate electrode being formed by alternatingly laminating on a silicon substrate a polysilicon layer and a tungsten silicide layer with a tunnel oxide sandwiched between said substrate and said polysilicon layer. The tungsten silicide layer is formed with a CVD technique reducing WF.sub.6 gas with SiH.sub.2 Cl.sub.2 gas.Type: GrantFiled: September 17, 1992Date of Patent: November 9, 1999Assignee: Sharp Kabushiki KaishaInventors: Yasuhiro Koyama, Hiroshi Ishihara
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Patent number: 5951069Abstract: A door closer device includes an active lever which, when it is in an abnormal state-with respect to a latch lever, automatically returns a door to a normal state by means of a door closing operation. An active latch which is pivotably supported by an active lever is freely rotatable in one direction, but is rotation regulated by an arm of an active pawl, i.e. a cancel lever, in the other direction. This prevents the latch lever from jumping over the active latch and causing an abnormal state in which the active latch swings wide with respect to the latch lever.Type: GrantFiled: April 24, 1997Date of Patent: September 14, 1999Assignee: Aisin Seiki Kabushiki KaishaInventors: Norikazu Kobayashi, Hiroshi Ishihara, Hiroyuki Mizushima, Ryujiro Akizuki
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Patent number: 5944367Abstract: An apparatus for perfectly closing a door of a vehicle basically comprising a latch, a pawl, a motor, an active lever, a latch lever, a pawl switch, and a latch switch. The door closing begins with the action of the latch moving from the door half-closed to the closed position an shown by the switching off of the pawl switch with the latch switch turning on. The electric motor activates upon detecting the door half-closed position and stops when the closed position is reached.Type: GrantFiled: April 24, 1997Date of Patent: August 31, 1999Assignee: Aisin Seiki Kabushiki KaishaInventors: Tomoaki Imaizumi, Eiji Itami, Hiroshi Ishihara, Norikazu Kobayashi, Hiroyuki Mizushima, Ryujiro Akizauki
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Patent number: 5822239Abstract: The invention is directed to a writing method to effectively suppress inter-cell interference when writing data to a single transistor type ferroelectric memory. When V is a writing voltage, stripe-like conducting electrodes are row electrodes, and semiconductor stripes are column electrodes, then the writing method includes a first procedure and a successive second procedure based on V/3 rule. In the first procedure, when a voltage of +V is applied to the row electrode of the cell being observed, while a voltage of zero is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of +(2/3)V are applied to the other column electrodes, then in the second procedure, a voltage of zero is applied to the row electrode of the cell being observed, while a voltage of +V/3 is applied to the column electrode, and voltages of +V/3 are applied to the other row electrodes, and voltages of zero are applied to the other column electrodes.Type: GrantFiled: July 10, 1997Date of Patent: October 13, 1998Assignee: Tokyo Institute of TechnologyInventors: Hiroshi Ishihara, Eisuke Tokumitsu
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Patent number: 5619494Abstract: The single port of a concentrator is branched into a plurality of ports by connecting a connector for the former-stage connector to the port of the concentrator and connecting the former-stage connector of the same structure in the other access unit to the connector for the latter-stage circuit to thereby cascade a plurality of access units. The LAN is expanded by connecting the workstation to the port connector of each of the cascaded access units. The thus, connected workstations provide an overlap signal of an AC signal and a DC signal. DC signal extraction circuit in the access unit extracts the DC signal from the overlap signal. A relay drive circuit is operated by the DC signal so that a relay is switched to the port connector side and the circuit is then connected to the workstation.Type: GrantFiled: September 15, 1994Date of Patent: April 8, 1997Assignee: Mitsubishi Cable Industries, Ltd.Inventors: Toshiyuki Nishikawa, Hiroshi Ishihara
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Patent number: 5580904Abstract: According to the present invention, a novel compound group which can pass through blood-brain barrier (BBB) with carrying a drug thereon and stay within brain to release the drug and a well-known compound group having the properties described above are provided.The compound represented by the general formula ##STR1## wherein, R.sup.1 represents C.sub.1-6 alkyl which may be substituted by a group selected from hydroxyl, carboxyl, amino group which may be substituted by C.sub.1-6 alkyl, and a five- to seven-membered saturated heterocyclic ring,R.sup.2 represents hydrogen or C.sub.1-6 alkyl,R.sup.3 represents hydrogen or C.sub.1-6 alkyl which may be substituted by hydroxyl,R.sup.4 represents hydrogen or C.sub.1-6 alkyl,R.sup.5 represents an amino acid residue, or --S--R.sup.6 or --CO--R.sup.6 wherein R.sup.6 represents C.sub.1-14 alkyl which may be substituted by a five- to seven-membered saturated ring; C.sub.Type: GrantFiled: June 24, 1994Date of Patent: December 3, 1996Assignee: Drug Delivery System Institute, Ltd.Inventors: Toyoaki Ishikura, Teruomi Ito, Takashi Kato, Kazutoshi Horie, Hiroshi Ishihara, Takashi Senou
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Patent number: 5519812Abstract: The present invention relates to a product-sum operation circuit element and a circuit for addition by weighting a number of signals input in one neuron circuit in a neural network, and can provide an adaptive-learning neuron circuit for changing an interval of output pulses by learning by connecting a simple pulse generating circuit consisting of capacitance, resistance, unijunction transistor and the like.A product-sum operation circuit element according to the present invention, includes an insulator substrate, a single crystal semiconductor thin film having a p-n-p or n-p-n structure in a lateral direction formed in the shape of stripes on the insulator substrate, a ferroelectric thin film deposited thereon for covering at least the semiconductor stripe structure, and a stripe-like electrode consisting of a metal or a polycrystalline semiconductor further formed thereon for intersecting the semiconductor stripes at a right angle or suitable angle.Type: GrantFiled: March 5, 1993Date of Patent: May 21, 1996Assignee: Tokyo Institute of TechnologyInventor: Hiroshi Ishihara
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Patent number: 5494321Abstract: A vehicle door locking assembly includes a housing, a latch member and a pawl member provided in the housing for holding a vehicle door in a closed position, a manually actuatable door opening member provided on the housing for rotational movement, and a rotatably mounted lift lever which is operatively connected with the latch member. A release lever is mounted on the door opening member for rotational movement between a first position in which the release lever engages the lift lever so that rotational movement of the door opening member is transmitted through the release lever and the lift lever to the pawl member to release the door and a second position in which the release lever cannot engage the lift lever so that rotational movement of the door opening member is not transmitted to the lift lever.Type: GrantFiled: August 25, 1993Date of Patent: February 27, 1996Assignee: Aisin Seiki Kabushiki KaishaInventors: Hiroshi Ishihara, Yoshinobu Ogura
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Patent number: 5466021Abstract: A door closing device comprises a door-lock mechanism provided between a door and a body and including a striker secured to the body and a latch member provided on the door, a driving mechanism, and a door-closing mechanism for establishing a perfect closed condition of the door relative to the body when the striker is in receipt of a groove of the latch member. The door-closing mechanism includes a passive-lever adapted to be moved in a linear mode by the driving mechanism in order to be brought into engagement with the latch member.Type: GrantFiled: July 30, 1993Date of Patent: November 14, 1995Assignee: Aisin Seiki Kabushiki KaishaInventors: Hiroshi Ishihara, Yoshinobu Ogura
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Patent number: 5454607Abstract: A door closing device comprises a door-lock mechanism provided between a door and a body and including a striker secured to the body and a pawl provided on the door, a driving mechanism, and a door-closing mechanism for establishing a fully closed condition of the door relative to the body, the door-closing mechanism including an active-lever operatively connected to the driving mechanism, a passive-lever operatively connected to the door-lock mechanism, and a cancel-lever disposed between the active-lever and the passive-lever. The cancel-lever is rotatable relative to one of the active-lever and the passive-lever so as to be brought into engagement with a portion of the other of the active-lever and the passive-lever.Type: GrantFiled: July 30, 1993Date of Patent: October 3, 1995Assignee: Alsin Seiki Kabushiki KaishaInventors: Hiroshi Ishihara, Yoshinobu Ogura
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Patent number: 5322810Abstract: A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portion as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the surType: GrantFiled: February 9, 1993Date of Patent: June 21, 1994Assignee: Sharp Kabushiki KaishaInventors: Akitsu Ayukawa, Hiroshi Ishihara, Shigeo Onishi
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Patent number: 5303199Abstract: An easily circuit-programmable semiconductor device which comprises a dynamic random access memory (DRAM) unit, a redundancy circuit and a connection between them, the DRAM unit having as a capacitor a dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer and the connection having, as a member for programming the redundancy circuit, an electrically breakable dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer.Type: GrantFiled: February 19, 1991Date of Patent: April 12, 1994Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Ishihara, Makoto Tanigawa
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Patent number: 5299151Abstract: A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.Type: GrantFiled: June 18, 1991Date of Patent: March 29, 1994Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Ishihara, Kenichi Tanaka, Keizo Sakiyama
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Patent number: 5299152Abstract: A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.Type: GrantFiled: January 28, 1992Date of Patent: March 29, 1994Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Ishihara, Kenichi Tanaka, Keizo Sakiyama
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Patent number: 5285959Abstract: An air heating apparatus such as a fan heater, a forced circulation type ware air heater, and, an air conditioner and heater, is operated while the amount of radiation is taken into consideration. Moreover, after a PMV value of the room to be heated is generated from the temperature, amount of radiation, etc. of the room to be heated, the burning amount, air flow and the like are controlled to make the PMV value 0.Type: GrantFiled: May 14, 1992Date of Patent: February 15, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayuki Nanba, Yoshikazu Matsuda, Akio Taki, Takashi Nishikawa, Hiroshi Ishihara, Masao Yoshikawa, Mitsuharu Tomioka
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Patent number: 5278784Abstract: A non-volatile programmable memory having:a plurality of unit cells disposed therein, each of said unit cells including an anti-fuse that can write in data by electrically breaking down an insulating film, a select transistor individually connected to said anti-fuse, and a wiring connected to each anti-fuse; andan auxiliary transistor connected between mutually adjacent unit cells, said auxiliary transistor having a source region and a drain region respectively connected between said anti-fuse and said select transistor together incorporated in mutually adjacent unit cells.Type: GrantFiled: November 24, 1992Date of Patent: January 11, 1994Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Ishihara, Norihiro Tokuyama, Masaru Yuki
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Patent number: 5217912Abstract: A method for manufacturing a semiconductor device providing steps of implanting impurity ions on the whole surface of a semiconductor substrate having a plurality of gate portions, in which side walls are formed on gate electrodes, by using the gate portions as masks, and then laminating a first insulating film, carrying out a first heat treatment to diffuse the impurities implanted in the substrate and to form an impurity diffusion layer between the gate portions, removing the first insulating film in a contact formation region which substantially includes the impurity diffusion layer, carrying out a second heat treatment to reduce crystal defects on the impurity diffusion layer and to laminate a second insulating film, which is made of the same material as that of the first insulating film, on the whole surface of the semiconductor substrate including the contact formation region again, and laminating a third insulating film on the whole surface and then carrying out a third heat treatment to flatten the suType: GrantFiled: June 28, 1991Date of Patent: June 8, 1993Assignee: Sharp Kabushiki KaishaInventors: Akitsu Ayukawa, Hiroshi Ishihara, Shigeo Onishi
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Patent number: 5179291Abstract: An access unit for a local area network with loop topology includes a pair of connectors, a relay circuit, a pair of transformers, a direct current signal extraction circuit, a constant current circuit, a controller, and a coil. With the above arrangement, when a workstation connected to the access unit generates a composite signal having a DC signal, used for driving the relay circuit, superposed onto an AC signal for data transfer, only the DC signal component is extracted by the direct current signal extraction circuit to be inputted into the controller of the access unit. The relay circuit of the access unit is then operated. Thus, the signal outputted from the workstation, the composite signal having the DC signal superposed on the AC signal, is applied to the concentrator, so that the DC signal contained within the composite signal activates the relay contact in the concentrator.Type: GrantFiled: October 2, 1990Date of Patent: January 12, 1993Assignee: Mitsubishi Cable Industries, Ltd.Inventors: Toshiyuki Nishikawa, Hiroshi Ishihara