Patents by Inventor Hiroshi Ohta

Hiroshi Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11124631
    Abstract: Disclosed herein is a rubber composition containing 100 parts by mass of a solid rubber (A), 0.1 to 50 parts by mass of a modified liquid diene rubber (B) having a functional group derived from a silane compound represented by the formula (1), and 20 to 200 parts by mass of a filler (C), the modified liquid diene rubber (B) satisfying (i) to (iii): (i) a weight average molecular weight (Mw) is not less than 1,000 and less than 15,000; (ii) a vinyl content is not more than 70 mol %; and (iii) an average number of functional groups per molecule of the modified liquid diene rubber (B) is 1 to 20.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 21, 2021
    Assignee: KURARAY CO., LTD.
    Inventors: Hiromi Maeda, Daisuke Koda, Hiroshi Kanbara, Satomi Ohta
  • Publication number: 20210280844
    Abstract: The present invention provides a viscous adhesive capable of retaining the shape of an electrode and allowing for production of an electrode for a lithium-ion battery having a structure in which the energy density of the electrode does not decrease. The present invention relates to a viscous adhesive for a lithium-ion electrode which allows active materials to adhere to each other in a lithium-ion electrode, the viscous adhesive having a glass transition temperature of 60° C. or lower, a solubility parameter of 8 to 13 (cal/cm3)1/2, and a storage shear modulus and a loss shear modulus of 2.0×103 to 5.0×107 Pa as measured in a frequency range of 10?1 to 101 Hz at 20° C.
    Type: Application
    Filed: April 20, 2018
    Publication date: September 9, 2021
    Applicant: SANYO CHEMICAL INDUSTRIES, LTD.
    Inventors: Tomoya OHTA, Kotaro NASU, Kenichi KAWAKITA, Takuya SUENAGA, Yusuke MORI, Yasuhiko OHSAWA, Yuki KUSACHI, Hajime SATOU, Hiroshi AKAMA, Hideaki HORIE
  • Patent number: 10998188
    Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 4, 2021
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyoshi Mishima, Hiroshi Ohta, Fumimasa Horikiri, Masatomo Shibata
  • Patent number: 10978588
    Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Hiroshi Ohta
  • Publication number: 20210066497
    Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.
    Type: Application
    Filed: March 5, 2020
    Publication date: March 4, 2021
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Hiroshi Ohta
  • Publication number: 20200362303
    Abstract: The present invention provides a method for expanding PGC/PGCLC, including culturing PGC/PGCLC in the presence of a phosphodiesterase 4 (PDE4) inhibitor and/or cyclosporine A, further in the presence of forskolin, and a method for inducing oocytes from PGC/PGCLC, including culturing PGC/PGCLC in the presence of bone forming protein (BMP) and retinoic acid (RA).
    Type: Application
    Filed: November 30, 2018
    Publication date: November 19, 2020
    Applicant: KYOTO UNIVERSITY
    Inventors: Mitinori SAITOU, Hiroshi OHTA, Hidetaka MIYAUHI
  • Publication number: 20200294895
    Abstract: A semiconductor device includes a die pad; a semiconductor chip mounted on a front surface of the die pad; a bonding layer placed between the die pad and the semiconductor chip; a first resin member being positioned between the bonding layer and the semiconductor chip; and a second resin member covering the semiconductor chip and the front surface of the die pad. The first resin member is provided along a periphery of the semiconductor chip. The bonding layer includes a first portion and a second portion. The first portion is positioned between the semiconductor chip and the die pad, and contacts the semiconductor chip. The second portion is positioned between the first resin member and the die pad.
    Type: Application
    Filed: August 14, 2019
    Publication date: September 17, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi OHTA, Shunsuke NITTA
  • Patent number: 10749022
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro Ono, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10720523
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Patent number: 10711784
    Abstract: Provided is an air compressor which exhibits improved reliability by resolving problems relating to drainage discharge defects, and exhibits improved energy efficiency. The air compressor comprises: a compressor body which compresses air; a compressed air flow path through which the compressed air from the compressor body flows; a heat exchanger which is provided to the compressor flow path so as to cool the compressed air from the compressor body; and a drainage pipe (62) which branches from the compressed air flow path so as to connect to the exterior, and through which drainage condensed from the compressed air cooled in the heat exchanger flows. A strainer (65) which removes foreign matter contaminating the drainage is provided to the drainage pipe (62). An on-off valve (66) at the downstream side of the strainer (65), and a pressure sensor (41) at the upstream side thereof, said sensor detecting pressure inside the drainage pipe (62), are each provided so as to resolve drainage discharge defects.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 14, 2020
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Hiroshi Ohta, Hideki Fujimoto
  • Patent number: 10685841
    Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 16, 2020
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
  • Publication number: 20200119142
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Syotaro Ono, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200091335
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, third, fourth, fifth, sixth and seventh semiconductor regions, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on another portion of the first semiconductor region. The fourth semiconductor region is provided in at least a portion between the first and third semiconductor regions. The fifth semiconductor region is provided between the first and fourth semiconductor regions. The sixth semiconductor region is provided on the third semiconductor region. The seventh semiconductor region is provided selectively on the sixth semiconductor region. The gate electrode opposes the second, sixth, and seventh semiconductor regions. The second electrode is provided on the sixth and seventh semiconductor regions.
    Type: Application
    Filed: March 4, 2019
    Publication date: March 19, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Syotaro ONO, Hideto Sugawara, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita
  • Publication number: 20200083320
    Abstract: A semiconductor device includes a semiconductor body including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first and second semiconductor layers are alternately arranged in a first direction along a front surface of the semiconductor body, and each include multiple portions arranged in a second direction directed from a back surface toward the front surface of the semiconductor body. The first and second semiconductor layers are configured such that, in an active region, a large/small relationship between amounts of the first conductivity type impurity and the second conductivity type impurity in the portions positioned at the same level in the second direction reverses at a center in the second direction of the second semiconductor layer, and in the terminal region, the large/small relationship reverses alternately in the portions arranged in the second direction.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 12, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Ohta, Syotaro Ono, Hideto Sugawara, Hisao Ichijo, Hiroaki Yamashita
  • Patent number: 10578107
    Abstract: Typical liquid-cooled compressors use the effective means of reducing no-load power by repeatedly starting and stopping an electric motor according to the amount of required air, but sufficient consideration has not been given to the fact that frequent starting and stopping of large-output electric motors leads to a decline in motor reliability. In order to solve this problem, a liquid-cooled compressor for circulating a liquid inside a compressor body using a pressure difference, and equipped with a cooling channel for circulating said liquid for cooling, configured so as to have an intake valve for adjusting the air intake of the compressor body, to change the amount of air taken in through the intake valve, and as a result, to perform a low-pressure operation during no-load operation at two levels of reduced operating pressure consisting of a value no less than a minimum circulation oil supply pressure and a low value.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 3, 2020
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Shigeyuki Yorikane, Hiroshi Ohta
  • Publication number: 20200058786
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.
    Type: Application
    Filed: January 7, 2019
    Publication date: February 20, 2020
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Hideto Sugawara, Hiroshi Ohta
  • Patent number: 10483350
    Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connec
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: November 19, 2019
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
  • Publication number: 20190348276
    Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 14, 2019
    Inventors: Tomoyoshi MISHIMA, Hiroshi OHTA, Fumimasa HORIKIRI, Masatomo SHIBATA
  • Publication number: 20190181010
    Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an
    Type: Application
    Filed: August 23, 2016
    Publication date: June 13, 2019
    Applicants: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru NAKAMURA, Tomoyoshi MISHIMA, Hiroshi OHTA, Yasuhiro YAMAMOTO, Fumimasa HORIKIRI
  • Publication number: 20190088738
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gat
    Type: Application
    Filed: February 22, 2018
    Publication date: March 21, 2019
    Inventors: Syotaro Ono, Hiroshi Ohta, Hisao Ichijo, Hiroaki Yamashita