Patents by Inventor Hiroshi Segawa

Hiroshi Segawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090120677
    Abstract: A wiring substrate for mounting electronic parts and a method for manufacturing the same are provided. The wiring substrate includes a substrate that includes a first surface, a second surface and a plurality of through-holes that extend through the substrate from the first surface to the second surface so as to define a plurality of inner walls respectively. The wiring substrate further includes an external conductor that is formed on at least one of the first surface or the second surface of the substrate. A through-hole conductor is formed on one of the plurality of inner walls so as to define a through-hole conductor space and so as to be electrically connected to the external conductor. Also included is a conductive post with first and second post ends, the first post end being positioned in the through-hole conductor space such that the first post end is in contact with and is electrically connected to the through-hole conductor, and the second post end projects out of the conductor space.
    Type: Application
    Filed: September 5, 2008
    Publication date: May 14, 2009
    Applicants: IBIDEN CO., LTD, OCTEC INC.
    Inventors: Toshihiro NOMURA, Hiroshi SEGAWA, Yoshifumi MIYAZAWA, Katsuya OKUMURA
  • Publication number: 20090078307
    Abstract: A three-pole two-layer photo-rechargeable battery has a laminated two-layered structure that includes a solar battery cell, a storage cell, and a common electrode therebetween. The solar battery cell has a structure wherein a photo-electrode, which has a photo-sensitized dye and a semiconductor layer on a conductive substrate with optical transparency, counters via a first electrolytic solution a common electrode that has a catalyst layer on a conductive substrate. The storage cell has a structure wherein the common electrode, which has a first conductive polymer layer on a conductive substrate on a side opposite the catalyst layer, counters via a second electrolytic solution a storage cell counter electrode that has a second conductive polymer layer on a conductive substrate.
    Type: Application
    Filed: March 25, 2008
    Publication date: March 26, 2009
    Applicants: THE UNIVERSITY OF TOKYO, NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Hiroshi Segawa, Yosuke Saito, Satoshi Uchida, Takaya Kubo, Satoshi Fujita, Tadayuki Isaji
  • Publication number: 20090052869
    Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.
    Type: Application
    Filed: October 29, 2008
    Publication date: February 26, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yoshinori MATSUURA, Hiroshi Segawa
  • Patent number: 7457525
    Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: November 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Matsuura, Hiroshi Segawa
  • Patent number: 7415761
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 26, 2008
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080189943
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: April 7, 2008
    Publication date: August 14, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080173473
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: October 19, 2007
    Publication date: July 24, 2008
    Applicant: IBIDEN CO., LTD
    Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 7023926
    Abstract: The stream converting apparatus includes a stream extracting circuit that extracts a second level data stream from a first format data stream, an error detecting circuit that detects an error included in the second level data stream output from the stream extracting circuit, a data correcting circuit that corrects the detected error to generate a proper-form second level data stream, and a multiplexer that multiplexes the corrected second level data stream to generate a second format data stream.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Matsuura, Hiroshi Segawa
  • Patent number: 6918002
    Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: July 12, 2005
    Assignees: Renesas Technology Corp.
    Inventors: Satoshi Kumaki, Tetsuya Matsumura, Hiroshi Segawa, Atsuo Hanami, Vasile Mosneaga
  • Patent number: 6907068
    Abstract: To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: June 14, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Segawa, Satoshi Kumaki, Yoshinori Matsuura
  • Patent number: 6792006
    Abstract: The data multiplexing device includes a header information memory storing header information, ES buffers holding encoded data of a plurality of media, an output buffer holding packetized data, and a transfer controlling unit controlling a transfer of the header information stored in the header information memory and the encoded data held in the ES buffers and writing into the output buffer as the packetized data. The transfer controlling unit can generate the packetized data simply by controlling the transfer of the header information stored in the header information memory and the encoded data held in the ES buffers, whereby the media multiplexing can be readily achieved.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Kumaki, Tetsuya Matsumura, Hiroshi Segawa
  • Publication number: 20040170387
    Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.
    Type: Application
    Filed: October 3, 2003
    Publication date: September 2, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yoshinori Matsuura, Hiroshi Segawa
  • Patent number: 6765961
    Abstract: An encoding device includes a processor unit controlling an overall operation and at the same time having a software for executing an audio encoding process, a video encoding unit to execute a video encoding process, a multiplex process unit to execute a system process and a timing control unit to generate a timing signal for activating an audio encoding process, a video encoding process and a system process, all of these elements are mountable on the same substrate. Each of a control process for controlling the audio encoding process, the video encoding process and system process is executed as an interrupt process. The processor unit includes an interrupt control circuit. The interrupt control circuit selects, based on a predetermined priority, one interrupt process corresponding to at least one generated timing signal.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 20, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Segawa, Satoshi Kumaki
  • Patent number: 6708246
    Abstract: A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an external processor. The interface detects the integrated processor accessing an external device and asserts a bus request. Thus the signal processing device can process data with a shorter cycle and thus more efficiently.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kazuya Ishihara, Hiroshi Segawa
  • Publication number: 20040025333
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 &mgr;m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: February 3, 2003
    Publication date: February 12, 2004
    Applicant: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20030147468
    Abstract: An image data coding apparatus includes: a memory interface which controls reading/writing of data from/to an external memory; an MPEG2 processing unit for performing a compression-coding process using a first compression ratio; and a coder/decoder which is provided between the MPEG2 processing unit and the memory interface, which performs a compression-coding process using a second compression ratio lower than the first compression ratio on data outputted from an image data coding unit to the external memory, and which performs a decoding process on data outputted from the external memory to the image data coding unit.
    Type: Application
    Filed: October 3, 2002
    Publication date: August 7, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tetsuya Matsumura, Satoshi Kumaki, Atsuo Hanami, Hiroshi Segawa
  • Patent number: 6591495
    Abstract: An opening is formed in resin by a laser beam so that a via hole is formed. Copper foil, the thickness of which is reduced to 3 &mgr;m by etching to lower the thermal conductivity, is used as a conformal mask. Therefore, an opening is formed in the resin and the number of irradiation of pulse-shape laser beam is reduced. Thus, occurence of undercut of the resin, which forms an interlayer insulating resin layer, can be prevented and the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: July 15, 2003
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 6516031
    Abstract: Element processors (PE00 to PE33) included in a processor array (7) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE00, PE02, PE11, PE13, PE20, PE22, PE31, PE33) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: February 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuya Ishihara, Atsuo Hanami, Tetsuya Matsumura, Satoshi Kumaki, Hiroshi Segawa, Yoshinori Matsuura, Stefan Scotzniovsky
  • Publication number: 20020188798
    Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.
    Type: Application
    Filed: January 24, 2002
    Publication date: December 12, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Kumaki, Tetsuya Matsumura, Hiroshi Segawa, Atsuo Hanami, Vasile Mosneaga
  • Publication number: 20020181600
    Abstract: The stream converting apparatus includes a stream extracting circuit that extracts a second level data stream from a first format data stream, an error detecting circuit that detects an error included in the second level data stream output from the stream extracting circuit, a data correcting circuit that corrects the detected error to generate a proper-form second level data stream, and a multiplexer that multiplexes the corrected second level data stream to generate a second format data stream.
    Type: Application
    Filed: April 24, 2002
    Publication date: December 5, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshinori Matsuura, Hiroshi Segawa