Patents by Inventor Hiroshi Segawa

Hiroshi Segawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4913557
    Abstract: A plurality of testing circuits formed of parallel registers are incorporated in a plurality of circuit portions constituting a data processing circuit, the circuit portions having different number of bits to be processed. Each parallel register comprises scan latch circuits and latch circuits. The sum of the number of the scan latch circuits and that of the latch circuits being equal to the number of output terminals of the circuit portion having maximum number of bits to be processed. Each scan latch circuit has a first input terminal connected to an output terminal of the corresponding circuit portion, a second input terminal connected to the input terminal of the circuit portion, and an output terminal connected to the input terminal of another circuit portion, respectively. The control terminals are connected together in each register to receive control signals.
    Type: Grant
    Filed: November 15, 1988
    Date of Patent: April 3, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Segawa, Hideyuki Terane
  • Patent number: 4910734
    Abstract: A plurality of testing circuits formed of parallel registers are incorporated between a plurality of circuit portions constituting a data processing circuit. Each parallel register comprises scan latch circuits whose number corresponding to the number of sets of input and output terminals of the circuit portion. A first input terminal of each scan latch circuit is connected to an output terminal of the corresponding circuit portion, a second input terminal is connected to an input terminal of the corresponding circuit portion, an output terminal is connected to an input terminal of another circuit portion, respectively, control terminals of the scan latch circuits are connected together in each register to which a control signal is inputted. The testing circuit serves to test the circuit portion or operate the circuit portion upon reception the control signal corresponding to the test mode or the operation mode.
    Type: Grant
    Filed: November 15, 1988
    Date of Patent: March 20, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Segawa, Hideyuki Terane
  • Patent number: 4829237
    Abstract: A semiconductor integrated circuit has a plurality of circuits (2 and 5) to be tested for verification of operation thereof and first, second and third scanning registers (1, 4 and 6) to be used for self-testing, and it further has a register (3) for delay. In operation, predetermined test data is inputted to each of the first and second scanning registers (1and 4) and then the first and second circuits (2 and 5) to be tested process those data simultaneously. Thus, testing time is saved. Although the time required for processing in the first circuit (2) to be tested is shorter than that in the second circuit (5) to be tested, the processed data can be obtained simutaneously by the delay function of the register (3).
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: May 9, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Segawa, Masahiko Yoshimoto
  • Patent number: 4797585
    Abstract: In a semiconductor integrated circuit, a pulse generating circuit comprises a delay circuit receiving a first signal and producing a second signal delayed with respect to the first signal. The delay circuit has a delay time which is variable by a control signal supplied from a control circuit. The first and the second signals are inputted to a logic circuit, which thereby produces a pulse having a duration corresponding to the delay time of the second signal with respect to the first signal.
    Type: Grant
    Filed: March 27, 1987
    Date of Patent: January 10, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Segawa, Tetsuya Matsumura
  • Patent number: 4313753
    Abstract: A process for producing a citric acid soluble potassium silicate fertilizer comprises a step for kneading a mixture consisting essentially of potassium carbonate, fly ash, pulverized coal, other necessary starting materials and a caustic potash solution as a binder and then granulating the kneaded mixture, a step for drying the granulated product to a nearly absolutely dry state, and a step for calcining the dried granular product, whereby a chemical reaction takes place between the potassium and the silicon present in fly ash to convert them into a citric acid soluble potassium silicate.
    Type: Grant
    Filed: June 13, 1979
    Date of Patent: February 2, 1982
    Assignee: Denpatsu Fly Ash Company
    Inventors: Hiroshi Segawa, Katsufumi Akizuki
  • Patent number: 4293523
    Abstract: A process for producing a citric acid soluble potassium silicate fertilizer comprises a step for kneading a mixture consisting essentially of potassium carbonate, fly ash, pulverized coal, other necessary starting materials and a caustic potash solution as a binder and then granulating the kneaded mixture, a step for drying the granulated product to a nearly absolutely dry state, and a step for calcining the dried granular product, whereby a chemical reaction takes place between the potassium and the silicon present in fly ash to convert them into a citric acid soluble potassium silicate.
    Type: Grant
    Filed: August 12, 1980
    Date of Patent: October 6, 1981
    Assignee: Denpatsu Fly Ash
    Inventors: Hiroshi Segawa, Katsufumi Akizuki
  • Patent number: 4246118
    Abstract: An apparatus for separating suspended solids from a liquid includes a tank, a floating bed of granular filter material held at the upper portion of the tank at the time of filtration, a feed pipe for feeding the liquid at a position between a filtering section and a sedimenting section, a hollow member or members which are arranged within the tank at a position below the position of the filter bed but above the position of the feed pipe, an air supply pipe which blows air up through the hollow member or members, thereby creating a turbulence required for effective backwashing, an arrangement for bringing the filter bed down to a position where the lowermost surface of the filter bed is held below a position substantially flush with the top end of the hollow member or members, a means for discharging a filtrate from the tank which is arranged in the top portion thereof, and a means for discharging a deposit of the suspended solids from the tank, which is equipped at the bottom portion thereof.
    Type: Grant
    Filed: June 6, 1977
    Date of Patent: January 20, 1981
    Assignees: Nippon Paint Co., Ltd., Mizuho Kogyo Kabushiki Kaisha
    Inventors: Masahisa Tada, Masahiko Kato, Tsuneo Ukita, Hiroshi Segawa, Masao Domoto, Kiyoteru Mori, Kazuhiko Ishii, Shinobu Horinouchi, Masami Tsuzuki, Eiichi Uemura