Abstract: A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.

Abstract: A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.

Abstract: Prior to the control of disk transportation, from each of plural incorporated disk drives, a changer controller acquires an identifier peculiar to the disk drive via a local bus line, and recognizes correspondence relationships between element addresses and the disk drives. In response to arrival of a first request command, the recognized correspondence relationships are sent to a computer system serving as the request source. Furthermore, in response to arrival of a second command, also each of the disk drives sends the identifier to the computer system serving as the request source via the SCSI controller.

Abstract: It is targeted to prevent picture quality deterioration in the output picture information proper to the interlaced scanned picture and that ascribable to interlaced scanning. To this end, a decimating inverse discrete cosine transform unit 5 applies inverse orthogonal transform to four low-range coefficients in the horizontal direction and eight coefficients in the vertical direction among the respective coefficients of an orthogonal transform block of the compressed picture information of the input high resolution picture.

Abstract: A sound absorbing-insulating structure for vehicles comprises a sound absorbing layer which contains cellulose fibers containing cotton yarns, pulp fibers, etc. and synthetic resin as principal components. The sound absorbing-insulating structure for vehicles, in which a content rate of the synthetic resin is in the range of 0.01 to 80 wt %, and a surface density is in the range of 0.2 to 3 kg/m2, is provided. This sound absorbing-insulating structure has the good sound absorbing-insulating characteristic and is light in weight and inexpensive in cost.

Abstract: An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers 23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27.

Abstract: In a semiconductor device having a plurality of memory cells, each of the memory cells includes a floating gate, a control gate, a source and drain, and a silicide layer. The floating gate is formed on a semiconductor substrate of a first conductivity type through a gate insulating film to be insulated from a surrounding portion. The control gate is formed on the floating gate through an ONO film. The source and drain are formed on the semiconductor substrate on two sides of the floating gate and doped with an impurity of a second conductivity type. The silicide layer is formed on a surface of at least one of the drain and source. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A reactance of a reactance element in a multi-layer circuit board apparatus is trimmed by cutting a portion of the circuit pattern of the reactance element with a laser beam. The reactance element is sandwiched between grounded layers. A coil circuit pattern having at least a hole therein may be provided as the reactance element. A side portion between the edge of the coil circuit pattern and the hole is cut with the laser beam to trim the inductive reactance. Cutting is effected while the circuit is operated and the operating condition such as an oscillation frequency is observed. A plurality of holes may be provided in the coil circuit pattern. The trimming amount of the inductive reactance is determined by the number of the hole subjected to cutting. The holes may have different sizes. The trimming amount is obtained by which one of the hole is subjected to cutting. The distance between the cut circuit pattern is equal to or larger than the thickness of the circuit pattern.

Abstract: A semiconductor memory device improves driving capability of bit select transistors without increasing a memory cell array in size, wherein first and second sub-bit lines are elongated along the direction of a bit line and in the reverse direction and are connected to a main bit line through first and second bit select transistors each being independently controllable and the first and second bit select transistors are disposed in a deviated manner without being adjacent to each other with respect to the direction of the bit line.

Abstract: A tetraalkylammonium hydroxide (TAAH) solution recovered from a development waste through separation therefrom of impurities such as photoresist is mixed with a surface-active substance to have the surface tension thereof adjusted to a desired one, and then reused as a rejuvenated developer. Thus, the surface-active effect (wetting properties) of the rejuvenated developer recovered from the development waste is properly adjusted and controlled, whereby fine photoresist patterns can be stably and effectively developed. Usable surface-active substances include surfactants, and dissolved photoresist contained in the development waste or a photoresist-containing solution such as a photoresist-containing treated solution derived therefrom.

Abstract: A tetraalkylammonium hydroxide (TAAH) solution recovered from a development waste through separation therefrom of impurities such as photoresist is mixed with a surface-active substance to have the surface tension thereof adjusted to a desired one, and then reused as a rejuvenated developer. Thus, the surface-active effect (wetting properties) of the rejuvenated developer recovered from the development waste is properly adjusted and controlled, whereby fine photoresist patterns can be stably and effectively developed. Usable surface-active substances include surfactants, and dissolved photoresist contained in the development waste or a photoresist-containing solution such as a photoresist-containing treated solution derived therefrom.

Abstract: The disclosed process for rejuvenation treatment of a photoresist development waste mainly containing a photoresist and tetraalkylammonium (TAA) ions comprises at least a simple membrane separation step of treating the photoresist development waste or a treated solution derived from the photoresist development waste with a nanofiltration membrane (NF membrane) to obtain a concentrate (NF concentrate) mainly containing impurities such as the photoresist and a higher-purity permeate (NF permeate) mainly containing TAA ions. The NF concentrate and/or the NF permeate, preferably the NF permeate, is desirably subjected to a step of concentration and refining by electrodialysis or electrolysis and/or a step of refining by ion exchange treatment, for example, with an anion exchange resin and/or a cation exchange resin in one of the H form and the TAA form.

Abstract: In order to achieve effective reduction of memory cell area in a contactless type non-volatile memory, the main bit lines ran zigzag in the column direction connecting the buried local bit lines in two adjacent columns of memory cell blocks alternately. This permits the number of main bit lines to be half, thereby reducing the pitch of the main bit lines with the result of reducing the memory cell area.

Abstract: In order to reduce the number of erase operations of a nonvolatile memory cell which stores a threshold voltage selected from among a plurality of threshold levels, a plurality of programming operations are implemented before an erase operation. That is, the programming operations are executed which respectively vary the threshold voltage of the memory cell to a different one of the plurality of threshold levels, or retain the previously stored threshold voltage of the memory cell. Thereafter, the memory cell is erased so as to return the voltage which is stored in the memory cell to a predetermined level, in response to all of the threshold levels having been used in the programming operations.

Abstract: The present invention relates to a booster circuit which uses multiple pump circuits to provide high voltages. The pump circuits are provided with an input voltage Vcc and are generally each made up of a diode and a capacitor. A node driving circuit provides driving signals to driving nodes and thereby to the pump circuits. The driving nodes are connected by a charge transfer switch which is selectively activated so as to allow charge that would otherwise be lost to ground to be conserved for inclusion in the final high-output voltage.

Abstract: There is provided a nonvolatile semiconductor memory which can simplify a circuit structure of a row decoder circuit to minimize an increase in chip size, and selectively supply a negative voltage to a word line. The nonvolatile semiconductor memory has a row decoder circuit section for selecting one of word lines in a memory cell array in response to an input address, and outputting a negative voltage or high voltage to the selected word line in accordance with a selected mode while outputting a ground potential to non-selected word lines.

Abstract: An electrically erasable and programmable read only memory device supplies first current from a precharging circuit through a first input node of a sense amplifier to a selected bit line to see whether a selected floating gate type field effect transistor passes the first current or block the first current, and a reference voltage generator supplies reference voltage to a second input node of the sense amplifier so as to produce a potential difference between the first input node and the second input node; the reference voltage generator supplies second current from a dummy precharging circuit through the second input node and a reference floating gate type field effect transistor to a ground line so as to produce the reference voltage at the second input node; and the reference floating gate type field effect transistor has an interconnection between the floating gate electrode and the control gate electrode so as to prevent the floating gate electrode from accumulation of electron.

Abstract: The disclosed process for rejuvenation treatment of a photoresist development waste mainly containing a photoresist and tetraalkylammonium (TAA) ions comprises at least the step of concentration of TAA ions by electrodialysis and/or electrolysis, and the step of removal of impurities ?(residual) photoresist, other anionic components, cationic components such as Na.sup.+, etc.! by adsorption thereof on an ion exchange resin (preferably an anion exchange resin and/or a cation exchange resin in at least one of the hydrogen ion form and the TAA ion form) through contact therebetween, whereby a high-purity solution of a tetraalkylammonium hydroxide reutilizable as a photoresist developer can be simply and efficiently regenerated and recovered from the photoresist development waste. The step of concentration by evaporation and/or reverse osmosis membrane treatment may desirably be taken at least before electrodialysis and/or electrolysis from the standpoint of treatment cost reduction.

Abstract: The invention relates to a sound insulating structure including low-density and high-density layers. The low-density layer has first and second fibrous layers and ranges from 0.5 to 1.5 kg/m.sup.2 in surface density. The first and second fibrous layers are respectively made of first and second thermoplastic synthetic fibers. The first and second fibers respectively have first and second single fiber diameters, each of which diameters is in a range of from 3 to 40 .mu.m, and first and second fiber lengths, each of which lengths is in a range of from 10 to 100 mm. The high-density layer is formed on the low-density layer and is made of an air-impermeable polymer material and has a surface density that is higher than that of the low-density layer and ranges from 1 to 10 kg/m.sup.2. The low-density layer is high in sound-absorption coefficient and at the same time low in spring constant. Therefore, the sound insulating structure becomes substantially improved in sound insulating capability.

Abstract: A non-volatile semiconductor memory configured to be able to write a multi-value information into a memory cell, comprises a memory cell array composed of a number of memory cell transistors. First and second write circuits receive first and second quaternary input data, and generate first and second writing bit line voltages having a level corresponding to the value of the first and second quaternary input data, respectively. A column selection circuit selects first and second bit lines from a number of bit lines of the memory cell array, in accordance with a row address signal, and for simultaneously supplies the first and second writing bit line voltages to the selected first and second bit lines, respectively, at the time of the writing. Thus, two items of quaternary data can be simultaneously written into two memory cell transistors included in memory cell transistors of one row selected by one word line.